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FPGA Synthesis
with Synplify Pro® software - Available in Hard Copy Only
This course material introduces the new user to the Synplify Pro
FPGA Synthesis product. The course will familiarize the student
with the FPGA design flow utilizing features of the Synplify Pro
product, enabling the student to actively create designs using the
Synplifiy Pro product
Topics Include:
- Project Management
- Synthesis
Concepts
- The Interactive
Text Editor with Error Cross-probing
- SCOPE® Graphical Constraints Entry
- The finite
State Machine Tools
- Mapping to
FPGA Technologies
- Debugging
with the HDL Analyst® option
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Advanced
FPGA Synthesis with Synplify Pro® software - Available in Hard Copy Only
This course material expands on concepts introduced in the "FPGA
Synthesis with Synplify Pro" training class. The focus will
be on complex design techniques and high-performance design.
Topics Include:
- HDL Coding
Techniques for Performance
- Complex Clocking
- Technology-Independent
Attributes
- Technology-Specific
Attributes
- Architecture-Specific
Tips and Tricks for:
- Altera
- Xilinx
- Support for
IP Cores
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Essential
VHDL RTL Synthesis Done Right
by Sundar Rajan
Price: $49.95
315 Pages
Published by S & G Publishing
Date Published: 01/1999
Softcover |
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Summary by
Sundar Rajan
This book provides a simple, hands-on approach to writing VHDL for
RTL synthesis. It follows a systematic, "how-to" style and instructs
readers on practical VHDL design. Although targeted primarily at
programmable logic designers, the techniques presented in this book
make it equally useful for those interested in real-world HDL design.
This book addresses two fundamental issues:
- The primary
purpose of a VHDL synthesis tool is to create hardware that matches
the results of simulation.
- VHDL's rich
descriptive capability provides many ways to describe hardware,
with varying results when synthesized.
You will learn
to write correct VHDL in a style that will positively impact both
the design process and the quality of the end result.
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Design By Example
by Ben Cohen
Price: $60
282 pages
Published by VHDL Cohen Publishing
Date Published: 2001
Hardcover
Summary
in PDF Format |
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| Real
Chip Design and Verification Using Verilog and VHDL
by Ben Cohen
Price: $80
400 pages
Published by VHDL Cohen Publishing
Date Published: January 2002
Softcover
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Click
here to order |
Summary by
Rahul Razdan, Cadence Design Systems
This book is one of the best investments that a logic designer can
make. We are certain that it will be of enormous value to all those
involved in HDL-based chip design for years to come
One of
the things that makes this book particularly important is that it
doesn't focus on just Verilog or VHDL, but rather on actual design
and simulation using examples from both languages
Concentrates
on common classes of hardware architectures and design problems,
and focuses on the process of transitioning design requirements
into synthesizable HDL code
Numerous examples of real-life
designs illustrated with VHDL and Verilog
Code is shown in
a way that makes it easy for the reader to gain a greater understanding
of the languages and how they compare...Ben also covers a critical
aspect for any real-life testbench creation: the use of transaction-based
verification techniques.
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