Synplicity's Synplify Premier software is the ultimate FPGA implementation environment. It provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting a single FPGA-based prototype. The Synplify Premier solution addresses the most challenging aspects of FPGA design including timing closure, logic verification, IP usage, ASIC compatibility, DSP implementation, debug and tight integration with FPGA vendor back-end tools.

Technology Independence

In today’s highly competitive market designers need the ability to choose the appropriate FPGA for a particular project. Switching tools between projects consumes time and energy that could be more effectively used on creating a better design architecture. Synplify Premier enables push-button re-targeting of RTL code to different device architectures and even different FPGA vendors so you can quickly determine the device that will best meet your requirements and budget.

 Physical Synthesis

The most challenging aspect of today's high density FPGA design is timing closure. It is increasingly difficult to meet aggressive timing goals with the same amount of effort that it took in previous generations of FPGAs. Synplicity invented graph-based physical synthesis to improve timing closure by representing preexisting wires, switches and placement sites within an FPGA as a detailed routing resource graph and then using this graph along side new synthesis algorithms that merge optimization, placement and routing into a single process. This methodology results in timing estimations that are highly correlated with final post-P&R timing. Having highly accurate timing during logic optimization ensures the correct critical paths are being optimized and significantly reduces design iterations and shortens development time.

DSP Friendly Synthesis

DSP functionality within FPGAs continues to rise. Synplify Premier has DSP-aware mapping technology to take full advantage of the dedicated DSP structures and memories built in to today's modern FPGAs. Synplify Premier is designed to work seamlessly with Synplicity's ESL synthesis tool (Synplify DSP).

RTL Debug

The Identify RTL debugger within Synplify Premier is revolutionizing hardware debug much in the same way that moving from an assembly language debugger to source-level debuggers revolutionized software debug.This RTL-based verification technology offers the fastest method of finding functional errors in a design by providing simulator-like visibility into a live, running FPGA with real-world stimulus.

RTL Code Analysis

Synplify Premier offers the ability to quickly analyze and enhance Verilog or VHDL code. This is accomplished by automatically generating graphical representations of a design directly from the RTL. Both a high-level (RTL) technology-independent diagram and technology-specific schematic diagram are created. Cross-probing between these views and the RTL source code allows designers to immediately view the actual implementation of their design and analyze it for further improvement.