Synplicity’s Synplify Premier software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance.  In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates the debug process and provides a rapid and incremental method for finding elusive design problems.

Articles about Synplify Premier
	Blaming the Button: Physical Synthesis Moves to Mainstream (FPGAJournal)
	Graph-based Physical Synthesis for FPGA Design (Embedded Control Europe)
	Synplifying Physical Synthesis: Going Graph-based with Synplicity (FPGA Journal)
	Unique Graph-based Physical Synthesis for FPGAs (SoC Central)

Product Literature

Synplify Premier Datasheet Military / Aerospace Brochure

White Papers

An Open IP Encryption Flow Permits Industry-Wide Interoperability Unique Graph-Based Physical Synthesis Technology For Fast Timing Closure and Performance of FPGA Designs Fast Timing Closure on FPGA Designs Using Graph-based Physical Synthesis