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Synplify® |
Synplify Pro® |
Synplify® Premier |
| Behavior Extracting Synthesis Technology® (BEST™) produces globally optimized designs in a fraction of the time required for traditional tools |
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| Comprehensive Language Compiler for supporting a wide range of Verilog and VHDL language constructs |
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| SCOPE® constraints editor for spreadsheet-like entry of design constraints for synthesis, place and route |
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| Integrated module generation for high-performing, area-efficient implementations of arithmetic/datapath functions |
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| Automatic RAM inferencing for technology independent RTL source code |
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| Integrated language-sensitive HDL source code editor with syntax checker |
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| Customized mapping software for each FPGA device family ensures optimal implementation in the target device and technology independence |
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| HDL Analyst®automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code |
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| Management of multiple design implementations for larger team-oriented design projects |
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| Mixed Verilog and VHDL support |
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| FSM Explorer for optimal implementation of encoding for finite state machines with a graphical state machine viewer |
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| Automatic re-timing (balancing registers across combinatorial logic) for improved performance |
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| Automatic register balancing of pipelined multipliers and ROMS for improved performance |
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| MultiPoint™ synthesis technology for modular and incremental design methodologies |
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| Timing knowledge of Altera Megafunctions and Xilinx CoreGen modules enables system-level optimizations for performance and area |
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| Formal Verification Mode enables compatibility with popular Formal Verification tools such as Conformal from Cadence and eCheck from Prover |
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| Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA |
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| Integrated RTL instrumentation and debug of a live, running FPGA |
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| Incremental RTL debug flow |
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| DesignWare®-compatible library for easy ASIC code migration into an FPGA for prototyping |
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| Graph-based physical synthesis for fast timing closure and a push-button performance boost |
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| Design Planner™ OPTIONAL product for guiding the physical
synthesis process with an RTL design plan (floorplan) and analyzing
routing results |
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