The Synplify DSP software is a unique ESL synthesis solution offering DSP hardware engineers and algorithm developers the most efficient way to get their algorithms into silicon for FPGAs and ASICs. The Synplify DSP synthesis technology offers significant advantages over traditional design flows and traditional DSP design tools. With a DSP modeling library that incorporates hardware abstraction and a powerful DSP synthesis engine, designers can focus on algorithm behavior, eliminate the burden of hand coding architectural optimizations, and explore system-wide RTL area/speed optimizations automatically from a single algorithm model, resulting in:

● Faster time to market – eliminates months of logic-level and architectural optimization and coding, and delivers high quality implementation that utilizes all advanced FPGA device resources and ASIC technologies

● Ease of use – the Synplify DSP library and modeling environment offers the easiest design capture experience for multi-rate and vector-based DSP algorithms.

● Portability and Design Reuse – easily create and manage algorithmic IP at a high-level and leverage this ROI across all FPGA and ASIC technologies.

● Lower Cost – rapid design exploration allows fast application-specific tuning and more optimal results.

● Lower Risk – more predictable design capture and implementation process with fast design capture and architectural exploration features.

Key Features:

• Capture Algorithmic IP Quickly At a Higher Level of Abstraction
• Rapid Architectural Exploration
• Faster and More Comprehensive Algorithmic Verification
• Automatically Implement Into FPGA and ASIC

Faster and More Comprehensive Algorithmic Verification

The Synplify DSP synthesis engine creates an HDL implementation that is bit and cycle accurate with the model, no matter what type of architectural optimization or target technology is used. This enables HW design teams to use the model as the golden source and maintain a single version of IP that can target all available and future device technologies. The easier modeling and analysis environment also enables more comprehensive verification to be created.

The Synplify DSP synthesis methodology enables:

• Guaranteed bit and cycle accurate HDL across all architectural optimizations and device technologies.
• Fully automated verification flow using the input/outputs of the model simulation.
• Automatic creation of an RTL test bench with batch files for Modelsim, ActiveHDL, and other simulators to use the model simulation I/O data to re-simulate using the RTL output. The same test bench can be used to verify gate-level netlists as well.
• Powerful prototyping capabilities - the same Synplify DSP model can target both ASIC and FPGA devices – no changes to the model are required.
• Maximal reuse of test bench and test vectors, eliminating error-prone test bench/vector reconstruction.

Rapid ASIC Prototyping

Synplify DSP speeds and simplifies verification using FPGA prototypes because your algorithm models can target FPGA or ASIC technologies while maintaining bit and cycle accuracy. This enables: