The Synplify DSP software is a unique ESL synthesis solution offering DSP hardware engineers and algorithm developers the most efficient way to get their algorithms into silicon for FPGAs and ASICs. The Synplify DSP synthesis technology offers significant advantages over traditional design flows and traditional DSP design tools. With a DSP modeling library that incorporates hardware abstraction and a powerful DSP synthesis engine, designers can focus on algorithm behavior, eliminate the burden of hand coding architectural optimizations, and explore system-wide RTL area/speed optimizations automatically from a single algorithm model. This results in the following benefits:

● Faster time to market – eliminates months of logic-level and architectural optimization and coding, and delivers high quality implementation that utilizes all advanced FPGA device resources and ASIC technologies

● Ease of use – the Synplify DSP library and modeling environment offers the easiest design capture experience for multi-rate and vector-based DSP algorithms.

● Portability and Design Reuse – easily create and manage algorithmic IP at a high-level and leverage this ROI across all FPGA and ASIC technologies.

● Lower Cost – rapid design exploration allows fast application-specific tuning and more optimal results.

● Lower Risk – more predictable design capture and implementation process with fast design capture and architectural exploration features.

Key Features:

• Capture Algorithmic IP Quickly At a Higher Level of Abstraction
• Rapid Architectural Exploration
• Faster and More Comprehensive Algorithmic Verification
• Automatically Implement Into FPGA and ASIC

Automatically Implement Into FPGA and ASIC

  The  Synplify DSP software’s powerful DSP synthesis engine allows the user to automatically create architecturally optimized HDL implementation of their algorithm models. By specifying constraints to the DSP synthesis engine, the engineer can create a range of architectures optimized for the target technology. The Synplify DSP synthesis engine includes:

• Automatic implementation of any Synplify DSP model into an FPGA or ASIC that is bit and cycle accurate to the model.
• Automatic application of system-wide optimizations for pipelining, folding, and multi-channelization, saving months of hand coding
• Automatic micro-architectural exploration resulting in the best implementation for math operations and IP cores like multipy, add, divide, CORDIC math, FIR, FFT, Viterbi Decoder
• Many options for technology characterization including Estimated Timing Mode for fast analysis, or Advanced Timing Mode for more precise timing analysis and optimizations.
• Flexible multi-rate clocking support
• Synthesizable Verilog and VHDL RTL code generation that is architecturally optimized for the target device technology.
• Automatic generation of the project, constraint, and other necessary files for logic synthesis in the Synplify Pro® and Synplify® Premier logic synthesis tools
• Popular FPGA device support from Actel, Altera, Lattice, and Xilinx
• ASIC device support
• Automatic creation of HDL test bench to verify bit and cycle accurate behavior of the HDL and gate-level RTL
• Advanced features for ASIC devices including:
  • ASIC technology characterizations used for DSP synthesis optimizations
  • Memory Extraction for flexible support of 3rd party memory IP
  • RTL Resolution for better support of downstream synthesis tools
  • Support for standard ASIC design flows like Cadence RTL Compiler and Synopsys Design Compiler