The Synplify DSP software is a unique ESL synthesis solution offering DSP hardware engineers and algorithm developers the most efficient way to get their algorithms into silicon for FPGAs and ASICs. The Synplify DSP synthesis technology offers significant advantages over traditional design flows and competing DSP design tools. With a DSP modeling library that incorporates hardware abstraction and a powerful DSP synthesis engine, designers can focus on algorithm behavior, eliminate the burden of hand coding architectural optimizations, and explore system-wide RTL area/speed optimizations automatically from a single algorithm model, resulting in:

● Faster time to market – eliminates months of logic-level and architectural optimization and coding, and delivers high quality implementation that utilizes all advanced FPGA device resources and ASIC technologies

● Ease of use – the Synplify DSP library and modeling environment offers the easiest design capture experience for multi-rate and vector-based DSP algorithms.

● Portability and Design Reuse – easily create and manage algorithmic IP at a high-level and leverage this ROI across all FPGA and ASIC technologies.

● Lower Cost – rapid design exploration allows fast application-specific tuning and more optimal results.

● Lower Risk – more predictable design capture and implementation process with fast design capture and architectural exploration features.

Key Features:

• Capture Algorithmic IP Quickly At a Higher Level of Abstraction
• Rapid Architectural Exploration
• Faster and More Comprehensive Algorithmic Verification
• Automatically Implement Into FPGA and ASIC

Rapid Architectural Exploration

  Synplicity’s vision for delivering on a truly effective ESL solution is to provide an architectural synthesis or DSP synthesis methodology from a high-level model. Although the user interface is simple and easy to use, many powerful optimization capabilities are leveraged in the flow to create optimized HDL and ensure it will synthesize into an optimized and accurate implementation. This includes a system-wide optimization engine and technology characterizations that are built into the tool. Also very important are the micro-architectural and inferencing capabilities that are an inherent part of the HDL coding and how the IP-level library blocks are implemented for given sample rates and architecture constraints.

The most powerful part of the DSP synthesis methodology is the ability to use a single algorithm model to explore the entire range of optimized architectures and device technologies.

The Synplify DSP synthesis methodology enables:

• User-controlled architectural optimizations that automatically create a range of pipelined and serialized architectures.
  • Retiming: automatically pipeline the data path to meet timing
  • Folding: reduce area using resource sharing and scheduling techniques
  • Multi-Channelization: auto replicate and reduce area using resource sharing and scheduling techniques
• Quick exploration of area and speed tradeoffs across a range of parallelized and serialized architectures and device technology variations.
• Target-aware micro-architectural optimizations for key IP blocks such as multipy, add, divide, CORDIC math, FIR, FFT, Viterbi Decoder FIR filters, and FFTs.
• Accurate timing estimations for FPGA devices due to advanced timing engine
• Area optimizations to automatically leverage multi-rate behavior to increase resource-sharing in slower clock domains resulting in huge area reduction for designs with high decimation or interpolation factors.
• Automatic inference and mapping of appropriate operations into on-chip resources of FPGAs including HW multipiliers, MACs, single-port and dual-port memories, FIFOs, and HW shift registers.
• Better performance and cost of the final product due to the ability to explore a broad range of implementations which leads to significantly better tradeoff choices.
• Time saving architectural and DSP synthesis methodology eliminates the huge efforts required for exploration in hand-coding HDL flow and represents orders of magnitude savings in productivity.

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