The Synplify DSP software is a unique ESL synthesis solution offering DSP hardware engineers and algorithm developers the most efficient way to get their algorithms into silicon for FPGAs and ASICs. The Synplify DSP synthesis technology offers significant advantages over traditional design flows and traditional DSP design tools. With a DSP modeling library that incorporates hardware abstraction and a powerful DSP synthesis engine, designers can focus on algorithm behavior, eliminate the burden of hand coding architectural optimizations, and explore system-wide RTL area/speed optimizations automatically from a single algorithm model, resulting in:

● Faster time to market – eliminates months of logic-level and architectural optimization and coding, and delivers high quality implementation that utilizes all advanced FPGA device resources and ASIC technologies

● Ease of use – the Synplify DSP library and modeling environment offers the easiest design capture experience for multi-rate and vector-based DSP algorithms.

● Portability and Design Reuse – easily create and manage algorithmic IP at a high-level and leverage this ROI across all FPGA and ASIC technologies.

● Lower Cost – rapid design exploration allows fast application-specific tuning and more optimal results.

● Lower Risk – more predictable design capture and implementation process with fast design capture and architectural exploration features.

Key Features:

• Capture Algorithmic IP Quickly At a Higher Level of Abstraction
• Rapid Architectural Exploration
• Faster and More Comprehensive Algorithmic Verification
• Automatically Implement Into FPGA and ASIC

Capture Algorithmic IP Quickly At a Higher Level of Abstraction

Synplify DSP software provides a technology-independent modeling environment that enables the rapid capture of DSP algorithm models that can automatically be implemented into FPGA and ASICs. The Synplify DSP Blockset library provides a high level of hardware and architectural abstraction that allows system and DSP designers to focus on algorithm behavior without sacrificing portability across different hardware or device technologies. The modeling environment also provides the right features to make design capture fast, concise, and as flexible as possible.

The Synplify DSP tool saves an order of magnitude of effort in the capture of implementable algorithms. Instead of creating multiple models and re-implementing them into HDL, designers can create one fixed-point multi-rate description in Synplify DSP and then automatically create optimized architectures into any silicon technology.

The Synplify DSP Blockset and modeling features include:

• Comprehensive IP library like FFT, Viterbi Decoder, DDS, CORDIC math functions, etc. enabling rapid creation in application-specific domains.
• Easy fixed-point quantization and analysis tools with up to 128-bit precision
• Comprehensive multi-rate support including multi-rate filtering
• Vector support allowing high dimensional signals and operations to be described in a single data path (up to 2048 in length)
• Automatic propagation of fixed-point data types, vectors, and sample rates as the designer instantiates and creates the model saving significant effort in starting designs
• M-control feature raises the abstraction level for control logic and state-machines allowing the use of M-language description with automatic quantization, persistent variables for storage, and software-like in-line debugging features.
• Black-Box feature support including easy insertion and cosimulation of existing RTL cores or IP from Altera Megacore, Xilinx Logicore, and other 3 rd party vendors.
• Leverages the powerful Simulink model-based design environment for simulation and graphical tools to analyze the algorithm behavior, waveforms, spectrums, etc. in both a graphical and Matlab scripting environment
• Fast, high-level simulation models
• User-extensible and customizable IP methodology
• Hardware and architectural abstraction which abstracts away logic design details like resets, enables, etc. and enables powerful architectural synthesis optimizations into HDL for a broad range of FPGA and ASIC targets.