Aldec Active HDL

Active-HDL is a completely integrated FPGA design and simulation environment for VHDL, Verilog or Mixed language designs. The Active-HDL product includes Block Diagram and State Machine Editors, Automatic Testbench Generation, Waveform Viewing and Editing, RTL and gate-level simulation.

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Cadence NC-Verilog & NC-VHDL

Cadence NC-Verilog Desktop and NC-VHDL Desktop simulators offer programmable logic designers best-in-class performance and features. Both Cadence desktop simulators are integrated with the Synplify® solution to enable a highly productive engineering environment.

Synopsys VCS

VCS® is the industry's most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™.