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HAPS-31 (Virtex-4) |
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HAPS-31, Synplicity's High-performance ASIC Prototyping System is equipped with a single Virtex-4 FPGA, is the smallest member in the HAPS-30 family. HAPS-31 is designed for all ASIC prototyping needs, including HW/SW co-development, proof-of-concept studies, IP development and end user evaluations. The flexibility allows the same board to be reused in several projects or configurations by replacing daughter boards containing I/O and custom subsystems.
The 20-layer board is carefully designed for maximum performance, with respect to signal integrity, speed and other critical issues.
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| Features: |
- 1 Xilinx Virtex-4 devices, LX40/80/100/160 or SX55
in FF1148 package
- 0.3–1.1 million ASIC gates on one HAPS-31 board
- Signaling rate: 1 Gbps LVDS, 600 Mbps single-ended
- 739 ordinary I/Os
- 714 I/Os (LVDS as an option) in 6 HAPS connectors
(boards with LX40 and SX55 have 595 I/Os)
- 25 GPIOs
(boards with LX40 and SX55 have 20 GPIOs)
- 1 external single-ended clock input
- 1 external differential clock input
- 1 external clock output
- 1 programmable clock generator
- 48 local clocks – differential or single-ended
- 3 I/O voltages
- 1 adjustable to 3.3, 2.5, 1.8 or 1.5 V
- 1 fixed to 3.3 V
- 1 fixed to 2.5 V
- 6 I/O regions
- Configuration via on-board FlashPROMs, JTAG or
CompactFlash (option, see CONF30)
- On-board temperature and voltage monitor
- Built-in self-test
- Battery backed-up encryption key
- Single 5V supply voltage
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| Contact us about HAPS: |
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"We have 3000 signals between two FPGAs, and it runs smoothly! This was achieved by HAPS great I/O flexibility and Certify's pin multiplexing feature."
- Mihai Munteanu, Development Engineer, Philips Semiconductors in Zürich, Switzerland
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