Synplify DSP offers DSP hardware engineers and algorithm developers
the most efficient way to get their algorithms into silicon for FPGAs and
ASICs. Synplify DSP uses a unique DSP Synthesis technology that offers
significant advantages over traditional design flows and competing DSP
design tools. With a DSP modeling library that incorporates hardware abstraction
and a powerful DSP synthesis engine, you can focus on algorithm
behavior, eliminate the burden of hand coding architectural
optimizations, and explore system-wide RTL area/speed optimizations
automatically from a single algorithm model. This results in significantly
faster time-to-market and achieves superior timing, area, and cost for
DSP algorithm-based IC designs.
Comprehensive DSP library with comprehensive multi-rate and vector math support
Easy fixed-point quantization and analysis tools
User-extensible and customizable IP methodology
DSP Synthesis engine creates
architecturally
optimized RTL implementation and testbench
Saves months of hand coding by automatic optimizations for pipelining, folding, and multi-channelization
Perform architectural exploration across a range of device technologies
Supports FPGA Devices from Actel, Altera, Lattice, and Xilinx
Synplify DSP v3.6 ASIC Edition
Adds ASIC technology support in addition to the FPGA devices above
Enables powerful prototyping capabilities - the same Synplify DSP model can target both ASIC and FPGA – no changes to the model are required.
Advanced features specifically for ASIC:
ASIC technology characterizations used for DSP Synthesis optimizations
Memory Extraction for flexible support of 3rd party memory IP
RTL Resolution for better support of downstream synthesis tools
Support for standard ASIC design flows like Cadence RTL Compiler and Synopsys Design Compiler
What's New in v3.6:
New IP Blocks: Reed-Solomon encoder and decoder
Expanded saturation and rounding now includes all 6 MATLAB rounding modes:
Ceiling, Floor, Convergent, Nearest, Round, Fix
Blocks updated: Add, Convert, FFT, FIR, FIR Engine, FIR Rate Converter, Gain, IIR, Mult, and RFIR
Other Block Enhancements:
Target-aware improvements and intra-block pipelining in the FIR
Improved precision and rounding in FFT datapaths
Improvements to DivMod and FIR folding
Advanced Timing Mode Enhancements for more accurate optimizations:
Better timing estimates using routing delays
Improved speed and area for Add, Mult, FIR, and general folding
Can now be run as an implementation option from the GUI
Faster run times and better memory utilization for designs up to 35,000 blocks
Introduced Pattern Folding for enhanced folding optimization capabilities:
Improves area by folding designs with identically configured blocks that form repeating patterns
Synplify DSP ASIC Edition includes improvement sin RTL quality and new technology support for 150nm, 110nm, and 65nm technologies
Various other improvements in the Synplify DSP Blockset and DSP Synthesis Optimization Engine
Expanded built-in design example set
Adds support for Mathworks R2007b
Adds support for Linux RHEL5
Synplify DSP MathWorks Package Requirements
The foundation for Synplify DSP is the powerful MATLAB (technical computing language) and Simulink (model-based design) simulation tools from the MathWorks.
Required Packages:
MATLAB® M-language environment for algorithm design
Products 