The Amplify® AccelArray™ Pro
product is the only Fujitsu-certified custom physical synthesis,
floorplanning, and analysis solution for AccelArray structured
ASIC architectures. From a single environment, a designer can create
AccelArray floorplans, perform AccelArray-specific physical synthesis,
interactively analyze and modify the design, and complete a legally
placed gates design ready for handoff to Fujitsu. The software
is the result of joint development between Fujitsu and Synplicity.
The Amplify AccelArray Pro solution provides an integrated flow
with Fujitsu's AccelBuilder software, and directly reads AccelArray
physical and logical libraries.
Highest Quality of Results and Predictability with Custom Physical Synthesis AccelArray Frames (masterslices) have a very specific architecture that requires custom physical optimization if your design is to meet timing in the smallest possible area. Unlike traditional ASIC synthesis tools, Amplify AccelArray Pro software uses architectural knowledge and makes optimum use of the specific physical resoures availble on the AccelArray Frame die. It creates a legal, routable, optimized placement for your design. Custom optimization algorithms implement a design with predictable performance, in the smallest possible area, saving you time and money.
Knowledge of available silicon resources, design rules, and the location of obstacles combined with careful consideration of utilization levels, wire lengths, and routing resources, allows the Amplify AccelArray Pro solution to create a circuit topology that has predictable routing delays and a design that can be routed. Synplicity's patented SNAP™ technology anticipates possible timing violations that might occur due to long routes along critical paths. The SNAP technology adjusts the circuit topology to remove the problem.
Quickly Close Timing
Amplify AccelArray Pro software combines finely tuned logic and placement optimization algorithms with an ability to measure true timing and area from a legal and routable placement. The benefits are:
Timing from your placed gates design closely correlates with the final routed design — Fujitsu can thus close timing after handoff. You no longer need to budget huge timing margins at the time of handoff or iterate with trial layouts.
Your placement is completely legal and free of signal integrity/DSM issues – the placement abides by AccelArray design rules. Amplify AccelArray Pro software’s patented SNAP algorithms anticipate and mitigate unpredictable routes, preventing signal integrity issues or design rule violations downstream.
Exceptional Performance, Density, and Productivity with Floorplanning and Physical Analysis
The Amplify AccelArray Pro solution provides an easy to use floorplan creation and editing environment from which an individual or teams of designers can quickly assemble, analyze, and improve their design.
Macros and memories can be easily and legally placed within the floorplanner.
Groups of designers can work on individual portions of the design in parallel and combine them using a block-based design flows, designating non-overlapping, top-level bounding boxes within the floorplan.
Congestion hot spots can be identified and fixed upfront using the Amplify AccelArray Pro product’s congestion and row/utilization map. A plethora of annotated schematic features, critical path displays, and reports are provided.
Physical constraints can be set to further improve results.
