The Synplify Premier solution is the industry’s ultimate FPGA implementation and debug environment. It provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes. The Synplify Premier software is a technology independent solution that addresses the most challenging aspects of FPGA design including timing closure, logic verification, IP usage, ASIC compatibility, DSP implementation, debug, and tight integration with FPGA vendor back-end tools.
Synplify Premier: The Ultimate FPGA Implementation and Debug Environment
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems. The Synplify Premier software advantages include:
technology and vendor independence
in-system debug
fast timing closure
RTL analysis
DSP-friendly synthesis algorithms
superior Quality of Results (QoR)
Reach Timing Goals Quickly with Graph-based Physical Synthesis
Today’s high-density FPGAs make it increasingly difficult for designers to meet their aggressive timing goals quickly. Synopsys' Synplify Premier product addresses the timing closure challenge with its patented Graph-based physical synthesis technology .
Graph-based Physical Synthesis offers:
patented technology
improved timing closure through estimations that are tightly correlated with final post place & route timing
90% of designs are within 10% of actual timing
assurance that correct critical paths are being optimized
significant reduction in design iterations and development time
Graph-based physical synthesis provides tight correlation to final timing
Find Bugs Quickly
The Synplify Premier software provides a rapid method of finding functional errors in FPGA designs by providing simulator-like visibility into live-running hardware. The methodology is based on technology found in the Identify® RTL Debugger - the first and only tool that allows designers to instrument and debug directly in RTL source code. Synplify Premier’s debugger technology provides designers with:
ability to add probes and trigger conditions in familiar RTL source code
ability to see sequence of captured results annotated in context to the RTL code
fast, incremental debug flow ability to bypass time-consuming iterations through place & route
DSP Friendly Synthesis
As DSP functionality within FPGAs continues to rise, the Synplify Premier software’s DSP-aware mapping technology takes full advantage of the dedicated DSP structures and memories built in to today’s modern FPGAs. The Synplify Premier tool’s DSP aware synthesis provides:
DSP-friendly synthesis algorithms
RTL DSP functions automatically mapped into vendors’ DSP hardware
tight integration with Synopsys' Synplify DSP software
ASIC Verification using Single FPGA-based Prototypes
As a part of Synopsys' Confirma ASIC/ASSP Verification Platform, the Synplify Premier solution offers the most comprehensive system for implementing single FPGA-based ASIC prototypes. Synplify Premier’s ASIC prototyping features offer:
System-Level Implementation and IP Integration
The System Designer™ capability, a key component of the ReadyIP program, allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices. The System Designer capability offers:
the use of Spirit IP-XACT Compliant IP
the ability to Configure And Interconnect IP For System
easy Drag & Drop Connectivity
easy Reuse Of In-house, Proprietary IP
Eclipse-based format
Access To Third Party IP for Evaluation and Download The ReadyIP Initiative is a program that simplifies the access, evaluation, and use of IP for FPGA-based system design. It is an encrypted design methodology for FPGA implementation that allows users to incorporate and easily integrate IP from several third-party vendors within their designs using Synopsys’ industry-standard synthesis environments, the Synplify Pro® and/or Synplify® Premier solutions. The ReadyIP initiative offers:
standards-based, accessible and secure IP distribution environment
easy-to-Use IP evaluation mechanism
IP configuration and assembly integrated into Synopsys' synthesis products
Products 