Home > Partners > ReadyIP > Become an IP Provider

The ReadyIP program gives IP Providers instant access to Synplicity’s installed base of thousands of FPGA users. Through Synplicity’s Synplify Pro and Synplify Premier IP browser, System Designer, users will be able to easily access and evaluate your IP. By rapidly integrating your IP into their designs, users will get quick feedback on function and timing while keeping the contents of your IP secure under evaluation.

Key Benefits

• Advertise and proliferate your IP to FPGA users
• Securely distribute synthesizable evaluation versions of your IP in order to generate interest and leads
• Users can quickly integrate your IP, which is formatted in the IP-XACT standard, by using the Synplify Pro and Synplify Premier solutions’ new System Designer capability
• IP can be implemented in the user’s FPGA of choice (Note: some IP providers may opt to provide multiple FPGA-specific version of their IP, tuned to particular FPGA architectures)

Third-party IP providers who wish to expand the use of their IP and are focused on high quality, FPGA vendor independent IP that is well supported, are invited to enlist in this program. Charter members of the ReadyIP program include: ARM, CAST, Gaisler Research, and Tensilica.

How The ReadyIP Evaluation Process Works

• Providers run scripts available from Synplicity to package their IP
• Encrypt the RTL for your IP using the ReadyIP use model
• Specify whether your IP is to be “black boxed” by the Synplify Pro/Synplify Premier solutions or an output netlist be generated to a desired  level of security
• You will generally package your IP in SPIRIT IP-XACT format
• Synplicity lists your ReadyIP in the Synplify Pro/Synplify Premier IP web browser
• New IP can be listed at any time and is immediately accessible
• The FPGA designer is referred to your website and you capture lead information prior to an evaluation download. Lead information can be prefilled by Synplicity into a form that you provide.
• Your evaluation IP is always downloaded from your website so that you are in control of the distribution.
• When FPGA designers evaluate your ReadyIP, they will:
• Access IP via the Synplify Pro or Synplify Premier IP browser interface
• Connect, integrate, and configure IP at the system-level and then securely synthesize it. Secure IP may alternatively and optionally be imported directly into any existing RTL level Synplify Pro or Synplify Premier synthesis project.
• Synthesize the design and view timing reports. As an IP provider, you can: designate whether the synthesis tool is to black box the IP in the synthesized netlist so that the IP remains invisible in the output netlist; or whether it is to be unencrypted and thus allow final implementation in an FPGA.

To join the program and immediately list your IP in the Synplify Pro and Synplify Premier IP browser, please contact readyip@synplicity.com. New IP providers can be dynamically added to the IP browser every day.