Build your own ASIC prototype using off-the-shelf hardware modules

PCI Express
Since late October there are two members of the HAPS family based on PCI Express, PCIE-1-KIT and PCIE-4-KIT. Both kits include a HAPS daughter board, a host interface board for the PC, and a cable to connect the two boards together. The host interface board and the cable are the same for the two kits, i.e. designed to handle 4 lanes.

Design files and instructions how to use a PCI Express Core from PLD Applications (PLDA) together with HAPS are also a part of a delivery.
     Furthermore, the PCIE-1-KIT comes with a Reference Design based on a netlist version of the PCIe x1 Core from PLDA. The design measures the transfer rate between a PC and a HAPS motherboard, and displays it on the PC monitor.

Customers who need to include a PCIe Core in their ASIC can purchase cores in both ASIC and FPGA format from PLD Applications.

For customers who don't intend to use a PCIe Core in their ASIC, but still need a communication link from PCI Express to HAPS, we can offer our Local Bus Interface, PCIE-1-LBI.

PCIE-1-LBI : Local Bus Interface for PCI Express x1

Several new products in the HAPS family

Just before Christmas three new daughter boards were released.
     ADC_1x1 is a combined analog-to-digital and digital-to-analog board, with two high speed (80 Msps) and two low speed ADC channels, as well as two low speed DAC channels.
The high speed ADC channels are designed for a wide variety of applications, including SW radio and IF/IQ demodulation.
      DVB-OUT_1x1 implements the physical layer 0 of an SPI output (Synchronous Parallel Interface) and an ASI-C output (Asynchronous Serial Interface on coaxial cable), according to the standard EN 50083-9:1998.
      LCD1_1x1 contains connectors for interfacing flat panel displays to a HAPS system. The daughter board is also equipped with four high speed RS-232 ports, one universal JTAG port, and one HAPS compatible GPIO port.

Last week a memory board with Flash PROMs was released. FLASH_1x1 contains two 512 Mbit NOR Flash PROMs, accessible as 8 or 16-bit wide words. Four boards can be stacked to increase capacity.

Last Friday the local bus interface for PCI Express was released. PCIE-1-LBI includes IP cores, drivers, software and design examples for transferring data between a PC and a HAPS system using PCIE-1-KIT.

More new exciting products in the HAPS family will be released before summer. Right now we are doing the final tests on a daughter board which will connect ARM Core Tiles with a HAPS motherboard.

Not so far away is another exciting product . . .

Alf Larsson - VP of Engineering

Alf Larsson has been appointed as VP of Engineering with responsibility for development of all our ASIC prototyping products. Alf has many years of experience as a design engineer and ASIC specialist at Ericsson as well as other companies. Most recently he served as VP of Engineering at SwitchCore, another high tech company. Alf will be instrumental as HARDI takes the next step in growing the company and hiring a number of electronic design engineers.

Alf Larsson - VP of Engineering