Build your own ASIC prototype using off-the-shelf hardware modules

HAPS-50
A New ASIC Prototyping Family with Xilinx Virtex-5 Devices designed to work with Synplicity's Total Recall™ technology

HAPS-52 is the first member in the new HAPS-50 family based on Xilinx Virtex-5 devices.

The board has a number of important new features including more I/O and inter-FPGA connections, a global bus, more I/O-voltage regions and a more flexible clocking scheme. In addition, new functions provide improved monitoring and self-test, and remote configuration and setup of the board.

HAPS-52 is equipped with two Virtex-5 LX330 devices, which gives a capacity of 4 million ASIC gates.

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ARM Core Tile Interface
The new daughter board CTI_2x2 allows an ARM Core Tile from the Versatile family to interface to a HAPS motherboard. The HAPS motherboard will effectively function as a custom base board for the Core Tiles. All peripherals can be implemented using boards from the HAPS family.

CTI_2x2 also contains a header for programming the ARM Core Tile, and a JTAG debug interface for the ARM RealView Multi-ICE® cable.

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This technical and educational half day seminar will provide you with practical information on achieving rapid and comprehensive ASIC Verification using multi-FPGA prototypes.

• March 29 - Kanata, Ontario
• April 19 - Austin, TX
• April 26 - Beaverton, OR
• June 14 - Longmont, CO

If you would like this seminar in your area, please let us know at:

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