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The Identify product revolutionizes hardware debug in the same way that moving from an assembly language debugger to source-level debugger revolutionized software debug. The Identify product is a debug-centric verification tool which offers the fastest method of finding errors in a design by providing simulator-like visibility into a live, running FPGA. It is the first and only tool that allows designers to instrument and debug directly in RTL source code.

 
Articles about Identify
Debug-centric verification speeds time to market (EETimes)
Overcoming FGPA Debugging Challenges (Chip Design Magazine)
Identify Your Bugs in Time (The Syndicated)

Features and Benefits:

  • Instrumentation and debug directly in RTL
  • Menu-driven assignments of watch points, breakpoints, and clocks
  • Multiple, configurable IICE™ instances
  • Cross-triggering between clock domains
  • Trigger on code branch statements
  • Complex trigger modes
  • Real world stimulus
  • Instrumentation does not impact design timing
  • Excellent support

Product Literature
Identify Datasheet
Military / Aerospace Brochure
Success Stories
Success using the Identify® Product at ETAS
Success using the Identify® Product at Foundry Networks
WhitePapers
Timing-Closure in High-End FPGAs: The Premier Solution
An Open IP Encryption Flow Permits Industry-Wide Interoperability
FPGA Design Verification: Techniques for Creating a Fully Functional Design
Unique Graph-Based Physical Synthesis Technology For Fast Timing Closure and Performance of FPGA Designs
Fast, Efficient RTL Debug for Programmable Logic Designs
Fast Timing Closure on FPGA Designs Using Graph-based Physical Synthesis
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