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Accelerating ASIC Verification Using High-density FPGAs

Synplicity and Xilinx Present A Technical Seminar:
New Approaches To Accelerate ASIC, ASSP and SoC Verification Using FPGAs

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Please complete the following information to register for this educational seminar:

Location:

	8 November 2007 Beijing, China Time: 1:00 PM – 6:00 PM Park Plaza Hotel 25 zhi Chun rd, Haidian District Beijing 100083 China Click here to download a Beijing, China registration form .pdf to fax	9 November 2007 Shanghai, China Time: 1:00 PM – 6:00 PM Howard Johnson Hotel 595 jiu Jiang Road Shanghai 200001 China Click here to download a Shanghai, China registration form .pdf to fax

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Please complete the following questions so we can better serve your needs:

What type of design are you primarily involved in?
ASIC Design
FPGA Design

Which best describes your job function (choose one)?
Board Designer
Verification Engineer
System Architect
Other

What is the primary verification approach used by your design team?
Simulation Tools
Formal Verification Tools
Emulation Systems
FPGA-based Prototypes
Other

How would your design team choose whether or not to use an FPGA-based prototype of your ASIC? (please choose the answer that best fits)
We always prototype
We decide project-by-project
We never prototype
Other

How big is in your current design?
<1m gates
1m-5m gates
5m-10m gates
>10m gates
Other

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