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Accelerating ASIC Verification Using High-density FPGAs

Synplicity and Xilinx Present A Technical Seminar:
New Approaches To Accelerate ASIC, ASSP and SoC Verification Using FPGAs

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Please complete the following information to register for this educational seminar:

Location:
	2 November 2007 Cambridge, UK The Trinity Centre 24 Cambridge Science Park Milton Road Cambridge CB4 0FN	11 October 2007 Paris, France(Presentations to be provided in French) Holiday Inn Paris-Orly Airport 4 Avenue Charles Lindberg Paris, 94656 France

	15 October 2007 Munich, Germany Arabella Sheraton, Westpark Garmischer Str. 2 80339 München, Germany	Date TBD Hertzliya, Israel Dan Accadia Herzliya Hotel Ramot-Yam 122 St. Herzliya Beach, 46851	23 October, 2007 Stockholm, Sweden Kista Entre, Stockholm Knarranäsgatan 7 Kista, Sweden

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Please complete the following questions so we can better serve your needs:

What type of design are you primarily involved in?
ASIC Design
FPGA Design

Which best describes your job function (choose one)?
Board Designer
Verification Engineer
System Architect
Other

What is the primary verification approach used by your design team?
Simulation Tools
Formal Verification Tools
Emulation Systems
FPGA-based Prototypes
Other

How would your design team choose whether or not to use an FPGA-based prototype of your ASIC? (please choose the answer that best fits)
We always prototype
We decide project-by-project
We never prototype
Other

How big is in your current design?
<1m gates
1m-5m gates
5m-10m gates
>10m gates
Other

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