Accelerating ASIC Verification Using High-density FPGAs

Synplicity and Xilinx Present A Technical Seminar:
New Approaches To Accelerate ASIC, ASSP and SoC Verification Using FPGAs

Overview:

The relentless pace in the advancement of IC process technology, now at 65 nanometers, has made it feasible to implement highly complex designs with several million gates operating at hundreds of MHz. This pace has been both a blessing and a challenge. With higher gate counts, it is now possible to realize highly complex designs that encompass an entire system on a chip (SoC) in a single ASIC device. The challenge that comes with these higher gates counts is validating the intended functionality prior to committing the design to silicon.

Due to short product life cycles, a limited window of market opportunity and the costs involved, re-spinning a dysfunctional ASIC/SoC is not an option.

This technical and educational seminar, hosted jointly by Synplicity, Inc., and Xilinx, Inc., will discuss and compare different verification methodologies and will present justification for why the use of FPGA-based prototyping can save you valuable time and money on your current or future ASIC, ASSP or SoC projects.

What you will learn:

• Choosing the right FPGA device
  • Device features and capabilities suitable for Prototyping
  • Matching the right FPGA Technology to the design requirements
• Conditioning the design for FPGA
  • Making the ASIC design FPGA ready
  • ASIC design style vs. FPGA design style
• Getting onto the board
  • Board-design considerations
  • Build-your-own vs. off-the-shelf boards
• Debugging the design
  • In system Debug
  • Enhancing visibility
  • Fixing bugs and quick design iteration
• Alternatives To Full ASIC Production

Event Locations (click below to go to the registration page for that region):

Europe:

• Eindhven, Nederlands
• Cambridge, UK
• Stockholm, Sweden
• Paris, France
• Munich, Germany
• Hertzliya, Israel

Seminar Agenda:

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