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Synplicity Presents A Free Technical Workshop:

“How to Implement Communications and Signal Processing Algorithms in FPGAs and ASICs using Synplify DSP”

 

Who should attend?

Engineers and managers in projects involving the design and implementation of DSP algorithms using a Matlab/Simulink model-based methodology and targeting implementation in FPGA and/or ASIC silicon.

Click on the links below to be taken directly to that section:

Overview:

Synplify DSP offers DSP hardware engineers and algorithm developers the most efficient way to get their algorithms into silicon for FPGAs and ASICs. Synplify DSP uses a unique DSP Synthesis technology that offers significant advantages over traditional design flows and competing DSP design tools. With a DSP modeling library that incorporates hardware abstraction and a powerful DSP synthesis engine, you can focus on algorithm behavior, eliminate the burden of hand coding architectural optimizations, and explore system-wide RTL area/speed optimizations automatically from a single algorithm model. This results in significantly faster time-to-market and achieves superior timing, area, and cost for DSP algorithm-based IC designs.

What you will learn:

This seminar introduces DSP synthesis and architectural exploration concepts that can make the algorithm design and implementation faster, more reliable, and achieve better results. The presentation introduces Synplify DSP and how it can be used on different design examples ranging from filters, forward error correction and a complete wireless modem. The demonstration will show Synplify DSP in a flow from a high-level design captured in Simulink all the way to implementation in RTL that targets implementation in FPGAs and ASICs.

Event Locations (click below to go to the registration page for that region):

California:

  • March 12th 2008
    Sunnyvale, CA

Seminar Agenda:

8:30 - 9:00am

Registration

9:00– 9:15

Introduction to Synplicity

9:15 – 10:00

Introduction to Synplify DSP

This presentation introduces the concept of DSP synthesis and how it is different from other methods of going from DSP algorithm specified in Matlab/Simulink to RTL code for hardware implementation. This discussion covers topics including design languages, the importance of a technology-independent flow, and automatic application of DSP synthesis optimizations.

10:00 - 10:15

Break

10:15 – 11:30

Synplify DSP Product Demonstration

Several examples will be shown to illustrate how designs are captured in the Synplify DSP library and verified using Mathworks’ Simulink. Design examples include a baseband processor for a QAM modem, a digital filter and digital down conversion employing multirate signal processing. Once the Synplify DSP model is captured and verified in Simulink, it will be optimized and implemented into RTL using the Synplify DSP synthesis engine. Synplicity RTL synthesis tools will be used to target FPGAs from a single model or algorithm description without ever changing the source algorithm. The demonstration will also show how Synplify DSP can be used to re-target implementation in ASIC silicon.

11:30 am

Questions and Answers

 

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