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Synplicity's TotalRecall Full Visibility Technology Tutorial at DATE 2007

Tuesday, April 17
13:00 – 14:30
Acropolis, Meeting Room Gallieni AB

Click here to Register!

We invite you to join us on Tuesday, April 17 to learn about a revolutionary new verification technology from Synplicity. We will present a 75 minute technical tutorial on this technology allowing you to gauge how it could help you in your current or future design projects.

The Story so far...

TotalRecall Full Visibility Verification Technology is a breakthrough announced by Synplicity in January to immediate high interest from the design community.

Here is a sample of analysts' thoughts so far...

"Those clever little rapscallions at Synplicity, Inc. have done it again – they've come up with an idea that's so elegant and clever it takes your breath away. I'm now slapping myself on the head saying: 'Of course – that's obvious – why didn't I think of that?'"SoCCentral

It's time to find out how TotalRecall Technology can help you.

During this tutorial at the DATE 2007 Exhibition on Tuesday, April 17, Synplicity Developers will gladly deliver technical details on TotalRecall and help you prepare for its use in your next FPGA or ASIC Verification project.

Click here for full agenda.

Those who do attend will be entered for a prize draw at the end of the meeting (must be present to win).

Please complete the following registration form to reserve your seat for this event. (Spaces are limited and Synplicity retains the right to refuse entry).

All fields are required.

First Name:
Last Name:
Title:
Company:
Address 1:
Address 2:
City:
State/Province:
Postal Code:
Country:
Phone:
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To help us ensure the maximum relevance of our presentation for our audience, we would be very grateful if you would answer the following questions:

How does your group use FPGA?
for low-volume production (less than 1000 units total)
for mid-volume prodcution (more than 1000, less than 10,000 units total)
for high-volume production (more than 10000 units)
only for prototyping

How many FPGAs do you typically design onto a board?
1
2
3
4
more than 4

Do you use pre-made boards including FPGA?
never, we always make our own boards
sometimes, we buy in eval boards or prototyping boards
always, we prefer to use boards as sub-systems

Which of the following would you most like to improve in your FPGA Design Flow (check all that apply)?
Device performance
Power consumption
Device resource usage
Achieving same performance after changes
Place and Route runtime
On-board Debug
System-Level Design

On a scale of 1 to 9, how would you rate your overall FPGA expertise (1 = beginner, 5 = sufficient, 9 = expert)?

 
 
 
 
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