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Visit Synplicity at DAC 2008
Booth No. 1310
Exhibit Dates and Hours:
Monday, June 9, 9:00 am 6:00 pm
Tuesday, June 10, 9:00 am 6:00 pm
Wednesday, June 11, 9:00 am 6:00 pm
Thursday, June 12, 9:00 am 1:00 pm
Synplicity is a leading supplier of innovative IC design and verification solutions. Synplicity’s FPGA implementation tools simplify, improve and automate logic synthesis, physical synthesis, analysis and debug for programmable logic designs. Synplicity’s ESL synthesis solutions significantly improve productivity for DSP designs realized in ASICs and FPGAs. The Confirma™ verification platform, comprising software tools and the HAPS™ family of prototyping systems, enables comprehensive verification of ASIC, ASSP and SoC designs and software development prior to chip tapeout.
Visit booth #1310 for in-depth demonstrations of the following Synplicity solutions:
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| Confirma ASIC/ASSP Verification Platform |
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Multi-FPGA Prototype Implementation With Certify
This demonstration will take you through the complete flow of partitioning an ASIC design into multiple FPGAs and implementing it in a HAPS prototyping system. You will also see how embedded software debugging tools are used to interact with an SoC design running in HAPS for software development and early hardware/software integration.
Full Visibility For FPGA Prototype Systems With Identify Pro
This demonstration will introduce the next generation of debugging and visibility enhancement tools for FPGA prototypes. Identify Pro with its award-winning TotalRecall technology, will be used to provide full visibility into the Design-Under-Test (DUT) running on a HAPS prototyping system, all without compromising on performance or functionality. Moreover you will see how VCS (software simulator) is leveraged as the design analysis and debug frontend.
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| ESL Synthesis Product |
| The Synplify DSP product demonstration uses a wireless transceiver example similar to Digital Video Broadcast (DVB) running on a HAPS-51 platform to illustrate the benefits of Synplify DSP's high-level modeling features, IP library, and architectural synthesis implementation flow for FPGAs and ASICs. |
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| FPGA Implementation |
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ARM ReadyIP Flow
This demonstration will showcase the complete system hardware and software development flow for users wishing to implement FPGA designs or verify ASIC designs that contain ARM microprocessors and the Amba2 bus. The full solution will be presented — from Synplicity's System Designer system-level design assembly and Synplify® Premier graph-based physical synthesis through final implementation on the Synplicity HAPS-51 high-speed prototyping hardware board. This demonstration will be complete with system software debug on the board using ARM Kiel and Realview software development and debug tools. ReadyIP from ARM and CAST (SOC Solutions) are used to demonstrate the Synplicity FPGA design and verification flow.
Tensilica ReadyIP Flow
This demonstration will show the complete system hardware and software development flow for users wishing to implement FPGA designs or verify ASIC designs that contain Tensilica microprocessors and the Amba2 bus. The full solution will be presented — from Synplicity's System Designer system-level design assembly and Synplify Premier graph-based physical synthesis through final implementation on the Synplicity HAPS-51 high speed prototyping hardware board. This demonstration will be complete with system software debug on the HAPS board using Tensilica’s software development and debug tools. ReadyIP from Tensilica and CAST (SOC Solutions) are used to demonstrate the Synplicity FPGA design and verification flow.
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Visit Synplicity at DAC 2008 to see how our products can help you achieve Simply Better Results®.
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