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Synopsys DesignWare Verification IP for SATA

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The Synopsys DesignWare® SATA verification intellectual property (VIP) provides a quick and efficient way to verify system-on-chip (SoC) designs having a Serial Advanced Technology Attachment (SATA) interface. DesignWare SATA Verification IP provides Device and Monitor models to verify compliance of a SATA Host interface with Serial ATA 2.5 specification. Native testbench (NTB), reference verification methodology (RVM), and functional coverage features are supported. These features allow users to rapidly create complex protocol test scenarios with DesignWare SATA VIP.

DesignWare SATA Complete Solution Datasheet
 

  • Compliant with Serial ATA 2.5 specification
  • Supports 1.5 Gbps and 3.0 Gbps data transfer rates
  • NTB, RVM, and functional coverage support
  • Multiple testbench and language interface
    • Verilog, VHDL and Vera®
  • Native command queuing
  • Port multiplier field
  • Protocol checking and transaction logging
  • Programmable monitor interrupts
  • Programmable error injection and detection
  • Includes protocol-based scenario generation
Serial ATA Gen I (1.5 Gbps) Gen II (3.0 Gbps) and SATA 6Gbps DeviceSTARsSubscribe
Serial ATA Gen I (1.5 Gbps) Gen II (3.0 Gbps) and SATA 6Gbps MonitorSTARsSubscribe

  Description Serial ATA Gen I (1.5 Gbps) Gen II (3.0 Gbps) and SATA 6Gbps Device
  Name sata_device_vmt
  Version 3.10a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type Verification IP Component
  Documentation
  Download dw_vip_sata
  Note OpenVera Compliant
  
  Description Serial ATA Gen I (1.5 Gbps) Gen II (3.0 Gbps) and SATA 6Gbps Monitor
  Name sata_monitor_vmt
  Version 3.10a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type Verification IP Component
  Documentation
  Download dw_vip_sata
  Note OpenVera Compliant