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For Immediate Release

SYNPLICITY-XILINX JOINT TASK FORCE DELIVERS REAL BENEFITS FOR ULTRA HIGH-DENSITY DESIGNS

Phase II Targets Area and Power Reductions with 65-Nanometer FPGAs

DESIGN AUTOMATION CONFERENCE, SAN DIEGO, June 4, 2007 – In their ongoing commitment to provide push button flows in 65 -nanometer (nm) FPGA design, Synplicity, Inc. (NASDAQ: SYNP), a leading supplier of software for the design and verification of semiconductors, and Xilinx, Inc. (NASDAQ: XLNX), the world’s leading supplier of programmable logic solutions, today announced an extension of their Ultra High-Capacity Joint Task Force activities to address area utilization and lowering power consumption.

For more than a year, both companies have worked closely to define and implement new solutions to maximize the quality of results and productivity for ultra high-density designs implemented in Xilinx 65-nm Virtex™-5 FPGAs. The first deliverable of the Synplicity-Xilinx joint task force (announced May 2006) was the development of SmartCompile™ Technology, an incremental design flow that improves run times by up to 6X while maintaining exact design preservation of unchanged logic. This RTL to place-and-route flow supports incremental changes so designers who need to make small modifications to an FPGA don’t have to recompile the entire device.

The initial phase of the Ultra High-Capacity Joint Task Force focused on providing dramatic improvements in overall quality of results and run time and ensuring the stability of results when incremental changes are made to an FPGA design. Phase II of the task force takes this progress to the next step — area reduction and lowering power consumption at 65-nm and below.

The overall goal of the joint task force is to provide designers with near push-button results for ultra high-density designs along with the ability to complete multiple design iterations per day. In view of the wide variety of applications enabled by ultra high-capacity FPGAs, the joint task force will deliver multiple design flows and tools optimized to meet the unique design requirements of these devices.

“We are pleased with the results of the first phase of our joint task force for improved incremental design,” said Ken McElvain, chief technology officer, Synplicity, Inc. “As the joint task force progresses, we expect it to continue to evolve to further address FPGA-based design and verification challenges — area and power reduction being among the top concerns voiced by our customers.”

“We’re looking forward to working closely with Synplicity on Phase II in our mutual design collaboration,” commented Bruce Talley, vice president of software, Xilinx, Inc. “This joint task force brings together our respective technology and engineering strengths to solve difficult problems through a unified solution. Synplicity and Xilinx intend to continue delivering solutions and products that provide our mutual customers with tools that better optimize designs for area and power on Xilinx 65-nm FPGAs.”

About Xilinx

About Synplicity

Synplicity® Inc. (Nasdaq: SYNP) is a leading supplier of innovative software solutions that enable the rapid and effective design of Programmable Logic Devices (FPGAs, PLDs and CPLDs) that serve a wide range of communications, military/aerospace, consumer, semiconductor, computer, and other electronic systems markets. Synplicity's tools provide outstanding performance, cost and time-to-market benefits by simplifying, improving and automating key design planning, logic synthesis, physical synthesis and verification functions for FPGA, FPGA-based ASIC verification, and DSP designers. Synplicity is the number one supplier of FPGA synthesis solutions and has been rated #1 in customer satisfaction since 2004 in EE Times' Annual FPGA Customer Survey. Synplicity products support industry-standard design languages (VHDL and Verilog) and run on popular platforms. The company operates in over 20 facilities worldwide and is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.

Forward-Looking Statements

This press release contains forward-looking statements including, but not limited to, statements regarding the performance, achievements and benefits of the Joint Task Force and developments stemming from the task force’s efforts. In some cases, you will be able to identify forward-looking statements by terminology such as “may,” “will,” “should,” “expects,” “can,” “believes” or the negative of these terms or other comparable terminology. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual results to differ materially from the forward-looking statements and changing technical requirements and customer demands in the FPGA and ASIC markets. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2006 and the quarter report on Form 10Q for the three months ended March 31, 2007, as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.

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Synplicity is a registered trademark of Synplicity, Inc. Xilinx, Virtex and SmartCompile are trademarks and registered trademarks of Xilinx, Inc.

Xilinx Press Contact: Tamara Snowden Xilinx, Inc. Public 408/879-6146 tamara.snowden@xilinx.com	Synplicity Reader Contact: Joe Gianelli Synplicity Inc. Marketing 408-215-6000 jgianelli@synplicity.com
Xilinx Press Contact: Mark Goosman Xilinx, Inc. Product 720/652-3426 mark.goosman@xilinx.com	Synplicity Press Contact: Nancy Sheffield Tsantes Consulting Group Relations 408/410-9928 nsheffield@tsantes.com