Synplicity Speeds FPGA Verification With Breakthrough
Incremental Debug For Xilinx Devices

Enhanced Identify Software Enables “Debug-Centric” Verification; Key Patents Issued for Its Debugging Technology

SUNNYVALE, Calif., April 12, 2004 — Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced it has enhanced its Identify™ RTL debugging software with major new features to extend its capabilities for FPGA and ASIC prototype hardware debugging. The Identify 2.0 software now features a fast and safe incremental flow for Xilinx FPGAs that allows designers to first debug specific signals in their hardware and then change those signals in a matter of minutes, thereby enabling a real-time, debug-centric verification approach. With this new RTL incremental flow, the available signals for incremental debug are automatically correlated back to the original RTL source code, taking the guesswork out of FPGA hardware debugging. This latest version of the Identify software also includes support for multiple sample clock views in a single debugger and an improved user interface with a debug project manager, making the tool able to handle complex designs in a more manageable way. Synplicity also announced two new patents, numbers 6,581,191 and 6,618,839, issued by the U.S. patent and trademark office covering the way the Identify technology debugs designs implemented in FPGA hardware using the original RTL source code.

One of the biggest problems with existing hardware debugging solutions is that when designers are not able to find the source of errors, they are forced to run multiple iterations of synthesis and debug insertion. This problem exists because it is difficult for designers to find errors in the post place and route netlist, often because the signal names have changed and there is no way to associate them back to the original RTL source. Because designers are forced to resynthesize the design and go through place and route again, several hours are added to every debug iteration.

“FPGA designers have a huge advantage due to the ability to switch to hardware based verification early,” said Ken McElvain, chief technical officer, Synplicity Inc. “The rapid increase in FPGA design size and complexity has threatened the productivity advantage of FPGA hardware-based verification by increasing the debug cycle time and making it harder to correlate post-synthesis signals with the original RTL design. With our Identify 2.0 software designers have RTL visibility into hardware and fast incremental change in the signals that are monitored, avoiding place and route cycles in design debug. This efficient debug-centric verification flow will yield a significant advantage for both ASIC prototypers and FPGA designers who are trying to reach their markets quickly.”

The incremental flow within the Identify software eliminates the guesswork of finding errors in the design by guaranteeing every signal available for incremental debug is correlated back to the original RTL source. Users wanting to view signals simply open the Identify software instrumentor and request the tool perform an incremental debug session. Instead of synthesizing the design again, the incremental debug session loads the original debug session, queries a database file and correlates the signals in the design to the place and route files — a process that typically takes only a few seconds. Once it is done, the tool displays the RTL source code, showing the signals it can correlate between the RTL and back-end database files. The Identify solution works closely with Xilinx’s back-end tools, enabling the software to go through incremental place and route in order to reprogram the FPGA.

“Synplicity’s Identify software has proven to be a unique and valuable tool for our customers,” said Rich Sevcik, executive vice president, Programmable Logic Systems Group and the Intellectual Property/Cores and Software Solutions Group at Xilinx. “The ability to do RTL debugging of hardware saves our customers a tremendous amount of overall design time. Now with the addition of the Identify software’s incremental flow, the tool provides a unique ability to debug an FPGA design in a fashion similar to using an RTL simulator but with the tremendous performance advantage of using the actual hardware.”

Increased Project Management
The latest version of the Identify 2.0 software includes a multiple sample clock feature and an improved user interface. With the multiple sample clock, or multi-IICE feature, the software enables designers to deal with multiple asynchronous clock regions in a single debugger window. Inside the debugger window, a user can have multiple tabs that relate to different clock regions within the design, allowing cross triggering between different clock regions. This allows designers to use complex triggering operations on a multi-clock design inside a single debugger window.

All new capabilities within the Identify software are managed under an improved user interface, offering significantly increased project and data management and making the tool easier to use. The instrumentor and debugger both have a project management feature inside the user interface that makes it much easier to load projects and data directly into the software. Another new feature of the software is the ability to save and load sets of trigger conditions allowing designers to save and reuse triggers much like stimulus in a simulator. Both the instrumentor and debugger software are now available for Redhat Linux 7.2, 7.3 and 8.0 as well as Windows 2000 and XP Professional platforms. The instrumentor software is also available on Solaris 7, 8, and 9 platforms.

Unique Technology Advantages
Identify is based on significant new technology that allows a design implemented in FPGA hardware to be debugged using the original RTL source code. Synplicity has already been issued two patents for this technology and has filed several additional patent applications. Synplicity believes this technology is a key differentiator that allows tremendous advantages in reducing the time required to find hardware design problems, allowing users to reduce their verification time by weeks or months.

Pricing and Availability
The Identify 2.0 software will be available in April 2004. Pricing for the Identify software starts at $9,000 (U.S.) for a one-year single vendor time-based license. Multiple vendor and perpetual licenses are also available. Additionally, copies of the Identify Lite™ software are currently being shipped along with the latest version of Xilinx’s Integrated Software Environment (ISE™) and are available for download from the Synplicity website. Identify Lite is a feature reduced version of the Identify 1.3 software that allows designers to test-drive most of the functionality of the full Identify software product. Users of the ISE design environment have access to a promotional software license of Synplicity’s Identify Lite software until August 31, 2004. For more information on the Identify software, visit Synplicity at http://www.synplicity.com.

About the Identify Software
Synplicity’s Identify software is the only software tool that allows FPGA and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs that is up to 10,000 times faster than RTL simulators and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. The Identify software allows designers to directly select signals and conditions in their RTL source code for debugging and viewing directly in the RTL source code. The software can also save results in standard VCD format that can be used with most waveform viewers.

About Synplicity
Synplicity® Inc. (Nasdaq: SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity’s high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, Structured/Platform ASIC and cell-based/COT ASIC designers. The company’s underlying Behavior Extracting Synthesis Technology® (BEST™), which is embedded in its logical, physical and verification tools, and has led to Synplicity’s top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company’s fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 270 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.

Forward-Looking Statements
This press release contains forward-looking statements including, but not limited to, statements regarding the capabilities and performance of the enhanced Identify software, both individually and used in conjunction with products from FPGA vendors, and Synplicity’s industry position. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual performance or
achievements of the enhanced Identify software to differ materially from those expressed or implied by the forward-looking statements. Such performance or achievements could differ materially due to a number of factors, including the performance and quality of Synplicity’s software products relative to other debugging software, latent defects, design flaws or other problems with the enhanced Identify software and the growth and changing technical requirements in the programmable semiconductor market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2003 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.

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Synplicity, Behavior Extracting Synthesis Technology and Synplify are registered trademarks of Synplicity Inc. Identify, BEST and Identify Lite are trademarks of Synplicity Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.

Reader Contact:
Brian Caslis
Synplicity, Inc.
408/215-6000
caslis@synplicity.com

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Porter Novelli
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