Synplicity Introduces First Router-Independent ASIC Physical Synthesis

Proven Correlation Across All Back-End Design Flows with SNAP Technology

DATE CONFERENCE, PARIS — February 17, 2004 — Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced the latest release of Amplify ASIC™ software featuring Synplicity’s new router-independent Sensitive Net Analysis and Prevention (SNAP) technology. The SNAP technology enables tight timing closure regardless of the backend router used. First, specific routes in the design that are susceptible to significant timing variations due to possible routing choices are identified. Once identified, circuit topology around these sensitive nets is modified to remove router choices that lead to poor results. Synplicity has filed patents for this technology, which will be available in all future versions of Synplicity’s ASIC physical synthesis tools (Amplify ASIC, Amplify® RapidChip® and Amplify® ISSP™ software solutions).

Need for “Best of Breed” Tools
“Most ASIC designers want the flexibility to use ‘best-of-breed’ tools together without the concern of interoperability problems,” said Ken McElvain, chief technology officer, Synplicity. “Other physical synthesis vendors have made their tools optimized only for their routing technology - in other words, suboptimal for other routing tools. Conversely, some vendors have sub-optimized their synthesis capability, with the claim that their specific placement and routing technology can reclaim the area or timing performance missed by their physical synthesis. We believe our SNAP technology directly addresses these issues by combining leading area and timing optimization technology with router-independent correlation to final GDSII.”

Synplicity’s SNAP technology also addresses the cost of complex ASIC design. Many design teams are looking today to incrementally improve their design flow, but cannot afford seven-figure retooling costs to move to a complete single-vendor flow. By using the Amplify ASIC software, designers can incrementally add to their existing design flows to move into high performance ASIC physical synthesis and leverage their existing physical design investments.

Sensitive Net Analysis and Prevention (SNAP) Technology
In performing physical synthesis on a complex ASIC design, a common issue for designers is that the final routing topology may be quite different from the routing topology assumed by the physical synthesis tool. Such topology mismatches account for wire-length and parasitics discrepancies, which result in substantial correlation and timing closure issues. The specific routes that are different between physical synthesis and final routing are referred to as ambiguous routes. Ambiguous routes are typically multi-fanout nets, where there are numerous possible topologies to connect the driver to all loads. Routes that cross-congest regions are also at risk, as they have to detour around the congested areas. Additionally, cross-talk induced delays typically put long routes at risk as well.
Synplicity developed algorithms that can identify ambiguous routes and compute their “sensitivity”. Sensitivity is a unique metric that assesses the timing impact of route ambiguity against the design constraints. Ambiguous routes that have high sensitivity must be addressed, as they endanger final correlation and timing closure. Synplicity has consequently developed specific physical optimizations that can remove ambiguity of sensitive routes, so that the final routing will match the routing assumptions used in physical synthesis. This new technology provides unique correlation and timing closure benefits regardless of the detail router used to finalize the design.

Pricing and Availability
The Amplify ASIC, Amplify RapidChip and Amplify ISSP software with SNAP will be available in March 2004 on Windows 2000/XP, Red Hat Linux, HP-UX, and Sun Solaris operating systems. A two-year term license for the Amplify ASIC software starts at $90,000 (U.S.), and a perpetual license of the Amplify ASIC software starts at $230,000 (U.S.). A one-year time-based license for the Amplify RapidChip and Amplify ISSP software starts at $35,000 (U.S.). For more information on the Amplify ASIC, Amplify RapidChip or Amplify ISSP software, visit Synplicity at http://www.synplicity.com.

About Synplicity
Synplicity® Inc. (Nasdaq: SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity’s high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, Structured/Platform ASIC and cell-based/COT ASIC designers. The company’s underlying Behavior Extracting Synthesis Technology® (BEST™), which is embedded in its logical, physical and verification tools, and has led to Synplicity’s top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company’s fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 270 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.

The specific features, functionality and release timing of any new technology or new versions of current products as described in this press release remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if such specific features, functionality or releases may occur.

Forward-Looking Statements
This press release contains forward-looking statements including, but not limited to, statements regarding the capabilities and performance of the new SNAP technology added to our ASIC tools and the expected benefits of such new technology. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual performance or achievements of the SNAP technology and the resulting enhanced ASIC software to differ materially from those expressed or implied by the forward-looking statements. Such performance or achievements could differ materially due to a number of factors, including the performance and quality of our ASIC software’s timing estimation relative to other ASIC synthesis software and the growth and changing technical requirements in the programmable semiconductor market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2002 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its new technology or enhanced software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.

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Synplicity, Synplify ASIC, Amplify, and Behavior Extracting Synthesis Technology are registered trademarks of Synplicity Inc. Amplify ASIC and BEST are trademarks of Synplicity, Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.

Reader Contact:
John Gallagher
Synplicity, Inc.
408/215-6000
johng@synplicity.com

Press Contact:
Steve Gabriel
Porter Novelli
408/369-1500
steve.gabriel@porternovelli.com