Synplicity Details Advanced Physical Timing Estimation Technology

Choice of Advanced Placement-Aware or Traditional Wireload-Based Timing Estimation

DATE CONFERENCE, PARIS — February 17, 2004 — Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced that it intends to offer timing estimation based on placement and automatic initial floorplanning as an alternative to traditional wireload model-based RTL synthesis in future releases of the Synplify ASIC® software. The company intends to offer this technology free of charge to customers who are under maintenance at the time of release. This new technology should help users reduce iterations between front-end and back-end design teams and provide more accurate estimates early in the design flow. Based on the vendor-proven placement and automatic floorplanning technology used in the Amplify ASIC™, Amplify® RapidChip™, and Amplify® ISSP™ synthesis tools, the Synplify ASIC software’s automatic placement-aware timing estimation will be optimized for fast runtime and small memory overhead.

“This technology is based on direct customer input,” said Ken McElvain, chief technical officer, Synplicity. “Additionally, we funded independent market research, including focus groups and conjoint analysis studies, which demonstrated that 70 percent of system designers who hand off their ASIC design to a backend team wanted synthesis and placement integration, but without having to become deeply knowledgeable about physical design and floorplanning. This market research also showed us that users viewed this as a natural evolution of standard RTL synthesis, and expect to have this feature provided under maintenance when released. With this announcement today, we believe we continue to demonstrate that we deliver high-value capabilities under maintenance such as power optimization (automatic clock gating); advanced datapath module generators; RTL, gate level, and placement level graphical debug environment (HDL Analyst® and Physical Analyst™); and automated RTL floorplanning.

Synplify ASIC Software Delivers Smaller Chips, Closed Faster
The Synplify ASIC software has been widely adopted for consumer and communications designs, with many customers citing its area reduction capability (see separate announcement today titled “Synplicity’s Synplify ASIC Adopted by Industry Leaders”). Customer results show the Synplify ASIC software can achieve up to 30 percent fewer gates than other synthesis tools, and have up to ten times faster runtimes. Additionally, the Synplify ASIC software takes better advantage of the complex cells in the vendor library, resulting in significantly fewer pin pairs needing to be routed. These existing capabilities in the Synplify ASIC product lead to faster layout runtimes. With the addition of placement-aware timing optimization, the Synplify ASIC tool is expected to offer both fewer and faster iterations for full design closure.

The advantages offered by Synplicity’s ASIC synthesis solutions apply to any size of ASIC design. Synplicity integrated ASIC placement technology in a way that does not significantly increase memory overhead. One design team using Synplicity’s integrated synthesis and placement technology was able to complete a 2.8 million gate design fully top down in less than a day, using a 32-bit operating system. The software also supports 64-bit Solaris and Linux operating systems for top-down operation of virtually any size of ASIC.

Placement Technology Within the Synplify ASIC Software
Synplicity has found that using timing based on an estimated placement instead of traditional wireload models in performing standard RTL synthesis can result in better correlation to final place-and-route results, even if the placement is not passed forward to the layout tools. The new timing estimation capability in the Synplify ASIC software includes both the global placer as well as the detailed placer currently available in the Amplify ASIC software. The placer uses a combination of analytical, mincut, iterative improvement and proprietary techniques for generating placement. Placement is based on an automatically generated initial floorplan. The global route estimation is done using an obstacle-avoiding Steiner tree heuristic. The wire delays are computed from the RC network, which is derived from the global route. Synthesis optimizations are integrated with placement estimation, global route estimation and P&R-aware delay estimation in generating an optimized netlist. Synthesis based on this improved timing correlation prevents over-optimization of circuit paths where wireload models would overestimate delay, saving area. Placement is used only for improved timing estimation and is not provided as an output of the tool. Users who want to create, analyze and debug placement of their ASIC are encouraged to use the Amplify ASIC software, which includes Synplicity’s Physical Analyst™ feature for placement-level design visualization.

About Synplicity
Synplicity® Inc. (Nasdaq: SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity’s high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, Structured/Platform ASIC and cell-based/COT ASIC designers. The company’s underlying Behavior Extracting Synthesis Technology® (BEST™), which is embedded in its logical, physical and verification tools, and has led to Synplicity’s top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company’s fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 270 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.

The specific features, functionality and release timing of any new technology or new versions of current products as described in this press release remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if such specific features, functionality or releases may occur.

Forward-Looking Statements
This press release contains forward-looking statements including, but not limited to, statements regarding the capabilities and performance of our enhanced Synplify ASIC software. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual performance or achievements of the enhanced Synplify ASIC software to differ materially from those expressed or implied by the forward-looking statements. Such performance or achievements could differ materially due to a number of factors, including the performance and quality of Synplify ASIC’s timing estimation relative to other ASIC synthesis software and the growth and changing technical requirements in the programmable semiconductor market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2002 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.

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Synplicity, Behavior Extracting Synthesis Technology, Synplify ASIC, Amplify and HDL Analyst are registered trademarks of Synplicity, Inc. BEST, Amplify ASIC and Physical Analyst are trademarks of Synplicity Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.

Reader Contact:
John Gallagher
Synplicity, Inc.
408/215-6000
johng@synplicity.com

Press Contact:
Steve Gabriel
Porter Novelli
408/369-1500
steve.gabriel@porternovelli.com