SYNPLICITY EXTENDS THE TIMING-DRIVEN ADVANTAGE OF ITS FPGA SYNTHESIS SOFTWARE FOR AREA AND COST REDUCTION

Synplify Pro Software Eases ASIC to FPGA Migration With Automated Gated Clock Conversion

SUNNYVALE, Calif., May 27, 2003 — Enabling designers the ability to further focus on area utilization and cost reduction, Synplicity, Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced it has further extended the timing-driven performance advantage of its FPGA synthesis software. With Synplicity’s unique true timing-driven approach to synthesis, the latest release of the Synplify Pro® software offers users the ability to more easily optimize for area after their speed goal is met, potentially reducing device size and saving tens to hundreds of thousands of dollars in device costs. Additional optimizations have also been added to the Synplify Pro software to further its performance quality of results (QoR), including the addition of register re-timing for Actel ProASIC and ProASIC Plus FPGAs as well as increased performance benefits for Altera Stratix devices and Xilinx Virtex-II Pro devices.

This latest Synplify Pro software release also features automatic gated clock conversion, eliminating the time consuming task of translating ASIC-based gated-clock elements into FPGA-based clock-enable structures. Additionally, the current software release also offers added support for Xilinx COREgen software and Altera clear box models, providing better timing estimation for IP blocks. With an expanded feature set that is optimized to increase area utilization, improve device performance and lower device costs, Synplicity’s enhanced version of the Synplify Pro software continues to offer the ease of use and the high quality of results that designers have come to expect from its Synplify® product line.

"We believe the performance benefits users can experience with this latest version of the Synplify Pro software will far exceed those of competing products,” said Jeff Garrison, director of marketing for FPGA products at Synplicity. “Today’s design managers are constantly looking for ways to cut design costs, and with our true timing-driven approach to synthesis, we believe users will be able to obtain significant area reduction in their devices, potentially saving tens or hundreds of thousands of dollars in device costs. Also, with the addition of automatic gated clock conversion, we have made it much easier for ASIC designers to efficiently and quickly target FPGAs without major HDL code changes.”

True Timing-Driven Synthesis Approach
With its enhanced true timing-driven synthesis approach, the Synplify Pro 7.3 software enables users to focus more on area utilization and cost reduction, while meeting their performance goals. Most FPGA synthesis tools optimize for area or performance, but don’t provide the ability to optimize for area once the speed goal is met at a global level. However, using the Synplify Pro software, designers are able to specify a timing frequency on their clocks, and once that frequency is met, the software automatically optimizes for less area, while continuing to meet the user’s performance targets. Synplicity believes this approach to synthesis enables optimal area reduction resulting in lower device costs.

Enhanced Timing Performance QoR
The Synplify Pro software now features automated register re-timing support for Actel’s ProASIC and ProASIC Plus device families. With re-timing, registers are automatically moved within combinatorial logic of the design to improve circuit performance. With the added re-timing feature, Actel device users can expect to experience an average of more than 15 percent performance improvements compared to previous releases without re-timing. The register re-timing feature within the Synplify Pro software also supports Xilinx and Altera devices.

"The Synplify Pro software’s register re-timing support for our nonvolatile, flash-based ProASIC and ProASIC Plus FPGA families will allow our customers to dramatically improve their device performance while shortening their development time,” said Saloni Howard-Sarin, tools marketing director at Actel Corp. “We believe using the Synplify Pro software in combination with our Libero integrated design environment ensures our customers their future design modifications will continue to meet their design specifications.”

Additional synthesis optimizations have been added to the Synplify Pro software to further enhance its timing performance QoR. Based upon results from a comprehensive test suite, Synplicity believes designers using Altera Stratix devices or Xilinx Virtex-II Pro devices along with the Synplify Pro software can expect to obtain on average a five percent device performance improvement over previous Synplify product releases and dramatically higher performance improvements over competing solutions.

Continuing to increase the ease of use of its FPGA synthesis solution, Synplicity included an automatic gated clock conversion feature within the software that enables users to efficiently migrate an existing ASIC design into an FPGA. With this feature, ASIC designs that have been written using gated clocks are automatically translated to clock enable structures in the target FPGA, significantly reducing the need for manual changes to the HDL code. This automated feature enables users to save days in the design process that would have been required to convert an average-sized ASIC into an FPGA.

The Synplify Pro software also offers support for Xilinx COREgen software and Altera clear box models, enabling designers to use more accurate timing estimates for IP blocks that were previously treated as black boxes. With this support, the timing information of an IP block created by the Xilinx COREgen software or an Altera clear box model is recognized by the Synplify Pro software so that logic around the IP can be optimized much more effectively in order to meet timing goals. This also results in a reduction of design iterations since the timing of the IP block is known, which results in fewer surprises after final implementation.

Pricing and Availability
The Synplify 7.3 and Synplify Pro 7.3 software will be available in mid-June. Pricing for the Synplify software starts at $9,500 (U.S.) and pricing for Synplify Pro software starts at $20,000 (U.S.).

About Synplicity
Synplicity, Inc. (Nasdaq: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company's industry-leading position, since the year 2000 Dataquest has named Synplicity as the #1 provider of PLD synthesis tools, announcing a 54 percent market share in 2001. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs), structured ASICs and system-on-chip (SoC) integrated circuits. The company’s fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of March 31, 2003, Synplicity employed over 260 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com.

The specific features, functionality and release timing of any new products or new versions of current products remains at the sole discretion of Synplicity, Inc., and no warranty is made as to when or if specific features, functionality or releases may occur.

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Synplicity, Synplify and Synplify Pro are registered trademarks of Synplicity, Inc. All other brands or products are the trademarks or registered trademarks of their respective owners.