Synplicity Details Strategy to Deliver a New Class of ASIC Physical Synthesis Technology

High-Performance, High-Capacity Physical Synthesis Technology to Provide Significant Area Reductions and Silicon cost Savings Over Existing Solutions

SUNNYVALE, Calif., April 22, 2003 — Delivering a fundamentally different approach to ASIC physical synthesis, Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced its strategy to develop ASIC physical synthesis technology which brings together the benefits of physical synthesis and silicon virtual prototyping into one tool environment. Synplicity believes its physical synthesis technology will be an ideal solution for the gate-level netlist handoff market — where designers pass their designs to either internal or external organizations for the back-end design work — and for the emerging “structured ASIC” market — led by Synplicity partners such as Lightspeed Semiconductor, LSI Logic and NEC Electronics.

Currently, ASIC designers must use two separate and disjointed technologies to achieve timing closure – silicon virtual prototyping to define a floorplan that can be physically implemented, and physical synthesis to deliver a gate level netlist along with a legal placement. This current approach has been difficult for many designers to use because of tool expense, learning curve and differences between results that can come from two separate environments. Synplicity has recognized that if the underlying synthesis, timing analysis and placement technology is extremely fast, both silicon virtual prototyping and physical synthesis can be performed together, resulting in better optimizations performed on the design in a fraction of the time required by using two separate environments.

Employing its core synthesis technology along with new placement, routing and automatic initial floorplanning technology, Synplicity will deliver ASIC physical synthesis that provides a high-performance, high-capacity solution to enable significant area reduction and reduce silicon costs. Unlike competitive solutions, Synplicity’s technology can operate on the entire design at once and perform fully automatic initial floorplanning followed by simultaneous RTL synthesis, clock tree estimation and placement to deliver a physically optimized gate-level netlist for project handoff, eliminating the need for a logic designer to become an expert in back-end design. Synplicity believes its high-performance, high-capacity approach will enable designers to achieve faster timing closure, higher accuracy and better area results. The new ASIC physical synthesis technology will leverage the company’s core synthesis algorithms as well as newly developed placement, routing and automatic initial floorplanning technology. Synplicity’s new class of physical synthesis technology will also be flexible based on users skill level, so that partial or full floorplans can be directly entered into and used in its physical synthesis flow. Synplicity believes that within a fraction of the time of other approaches, ASIC designers using Synplicity’s physical synthesis technology will be able to generate a final netlist and placement with high correlation to the final GDSII implementation of their design.

" We see a tremendous opportunity to deliver physical synthesis technology to the gate-level netlist handoff market — a group whose specific needs are largely unmet but that represent the majority of the ASIC design market who have chosen not to implement RTL to GDSII flows,” said Ken McElvain, chief technical officer at Synplicity. “As process geometries shrink, using physical synthesis technology is a requirement in enabling design teams to reduce area and achieve timing closure quickly. However, current solutions are unappealing to the majority of ASIC designers because of the degree to which they require a customer to become an expert in physical design, and the separation between physical synthesis and silicon virtual protoyping.”

According to Gary Smith, research vice president at Gartner, “The gate-level netlist handoff market is defined as designers who pass a gate-level netlist to an external organization, whether it be an ASIC vendor, a foundry partner or a separate team within the designer’s own company, to complete the back-end design work.” Designers in this space value the ability to achieve design closure and obtain accurate results quickly in order to minimize iterations between synthesis and physical design. However, as logic design experts, these designers want to focus on achieving the best results, requiring them to hand off their designs to physical design experts for completion.

Over the past few months, Synplicity and the Advanced Telecommunications Research Institute International (ATR) in Japan have worked closely to evaluate Synplicity’s floorplanning, placement and synthesis approach to ASIC physical synthesis against competitive physical synthesis methodologies. According to ATR, Synplicity’s physical synthesis technology was able to realize a 30 percent area reduction and achieved timing closure in a fraction of the time compared with other tools. ATR also found the timing results from Synplicity’s technology were more accurate versus final place and route compared to other solutions. Also key to ATR’s decision to select Synplicity was that its approach to ASIC physical synthesis allowed ATR’s design team to focus on achieving the best results, without the need to become experts in physical design.

The Emerging Structured ASIC Market
Synplicity has also recognized the emerging structured ASIC market as another opportunity to apply its physical synthesis technology. Structured ASIC devices are silicon in which the underlying pattern of logic cells, memory, third party IP and I/O are created ahead of time and are customized by application of the final few metal layers. These devices, such as the Lightspeed Semiconductor Luminance architecture, the LSI Logic RapidChip architecture and the NEC Electronics ISSP architecture, are aimed at the market space between advanced FPGAs and cell-based ASICs. In a separate press release issued today, Synplicity announced its intent to combine its physical synthesis technology with its expertise in developing custom mapping technology to deliver physical synthesis software optimized for the RapidChip architecture from LSI Logic.

About Synplicity
Synplicity Inc. (Nasdaq: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company's industry-leading position, since the year 2000 Dataquest has named Synplicity as the #1 provider of PLD synthesis tools, announcing a 54 percent market share in 2001. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs), structured ASICs and system-on-chip (SoC) integrated circuits. The company’s fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of March 31, 2003, Synplicity employed over 260 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com.

The specific features and functionality of new technologies as described in this press release remain at the sole discretion of Synplicity, Inc. and no warranty is made as to whether the specific features and functionalities will occur as described in the press release.

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Synplicity is a registered trademark of Synplicity, Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.

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Synplicity, Inc.
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