SYNPLICITY ANNOUNCES ASIC PHYSICAL SYNTHESIS SOFTWARE

Company Also Introduce Customized Physical Synthesis Software for LSI Logic's RapidChip Architecture

SUNNYVALE, Calif., May 27, 2003 — Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced a high-performance, high-capacity ASIC physical synthesis solution optimized for front-end designers targeting the cell-based ASIC, structured ASIC and platform ASIC markets. Leveraging Synplicity’s experience and success with highly automated, accurate and user-friendly synthesis technology, the new Amplify ASIC™ Physical Optimizer® software addresses many of the unmet needs of the majority of ASIC designers. Synplicity also announced today details of the Amplify® RapidChip™ Physical Optimizer® software, a single-vendor version of the Amplify ASIC software targeted specifically for LSI Logic’s RapidChip platform ASIC architecture.

Unlike previous physical synthesis products that address deep submicron timing closure issues by requiring logic designers to master complex physical design tasks, the Amplify ASIC and Amplify RapidChip physical synthesis solutions enable ASIC designers to rapidly and efficiently hand off a physically optimized gate-level netlist plus final placement to an ASIC vendor. By virtue of its high design capacity and fast runtimes, the software brings together the benefits of physical synthesis and silicon virtual prototyping into an integrated tool environment in order to deliver superior results and lower design costs. With this approach, logic designers are not required to become physical designers and are able to focus on their specific area of expertise.

"For several years now, EDA providers have been trying to push physical design tasks to front-end designers, claiming that this may be the only way to reach timing closure on aggressive designs,” said Ken McElvain, chief technical officer at Synplicity. “With the Amplify ASIC software, we demonstrate this is not the case. The Amplify ASIC software’s automation and advanced physical synthesis technology enable cell-based, structured ASIC and platform ASIC logic designers to deliver highly optimized designs and expect their ASIC vendor will not encounter timing closure issues after detailed routing. This way, logic designers can maintain their preferred hand off methodology, focus on their core competence and be more productive, turning more highly optimized designs in less time and at significantly lower design costs.”

Integrating Physical Synthesis and Silicon Virtual Prototyping In One Design Environment
The Amplify ASIC software is a physical synthesis solution for ASIC logic designers seeking the best timing and area optimization for their design. The software is based on Synplicity’s Behavior Extracting Synthesis Technology® (BEST™), algorithms which have been proven by dozens of Synplify ASIC customers to meet timing requirements while reducing the overall ASIC gate counts by up to 30 percent. This core technology is also capable of performing physical synthesis on multi-million gate ASICs with runtimes up to five to 15 times faster than previous physical synthesis tools. This foundation enables the combination of physical synthesis and silicon virtual prototyping into one tool environment, offering designers a highly automated, high capacity, high performance and accurate solution for achieving timing closure with a placed-gates hand-off to a back-end design team or ASIC vendor. For those who wish to get more involved in detailed physical design, the Amplify ASIC software’s ability to read and write industry standard DEF and PDEF formats assure ease of use with third party tools.

The Amplify ASIC software also includes fully automated initial floorplanning and clock tree estimation that helps accurately predict clock tree behavior, as well as built-in congestion analysis and placement algorithms. Using this technology, designers can rapidly and simultaneously synthesize, place and optimize an ASIC design up to 15 times faster than with traditional physical synthesis tools and with very high quality of results, correlating tightly to final placement and routing.

The Amplify RapidChip software is a customized version of the Amplify ASIC software that specifically targets LSI Logic’s RapidChip architecture. The Amplify RapidChip software is designed to be interoperable with LSI Logic’s design tools and libraries, enabling LSI Logic designers to cross probe seamlessly between the software and LSI Logic’s RapidChip design environment. The two companies are working closely so that the timing results will be highly accurate compared to final GDSII, thus enabling LSI Logic to provide a very fast turnaround time for final layout of the design. The Amplify RapidChip software brings designers a new class of physical synthesis software that enables designers to readily achieve design goals on RapidChip devices.

Design Capacity for 90nm
The Amplify ASIC software features a 64-bit operating system, providing the software with the capacity to synthesize an entire design of several millions of gates in one pass. After synthesizing and floorplanning a design from RTL code, the tool provides a gate-level netlist that is optimized for place and route as well as a legalized placement. By incorporating this top-down methodology, a designer avoids having to break up the design into separate blocks and manually synthesize each block, reducing design time and engineering resources. The fast static timing analysis capabilities within the Amplify ASIC software can process and analyze any size design in a fraction of the time compared to competitive solutions.

The Amplify ASIC software also features Synplicity’s unique Physical Analyst™ tool, providing rapid design debugging from placement and congestion views of the design to RTL source code and timing reports. By providing integrated design visualization and debugging across RTL, gate, placement and timing analysis views of a design, logic designers are able to rapidly and accurately pinpoint and remedy any design issues.

Pricing and Availability
The Amplify ASIC software will be available in the second quarter of 2003 and the Amplify RapidChip software will be available in the third quarter of 2003. The Amplify ASIC and Amplify RapidChip software run on Windows NT 4.0, Windows 2000, Red Hat Linux 8.0 and Solaris 2.7 operating systems. A one-year time-based license for the Amplify ASIC software starts at $90,000 (U.S.), while a three-year term starts at $130,000 (U.S.). A perpetual license of the Amplify ASIC software starts at $230,000 (U.S.). A one-year time-based license for the Amplify RapidChip software starts at $35,000 (U.S.), and a six-month time-based license is also available starting at $20,000 (U.S.). For more information on the Amplify ASIC or Amplify RapidChip software, visit Synplicity at http://www.synplicity.com.

About Synplicity
Synplicity Inc. (Nasdaq: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company's industry-leading position, since the year 2000 Dataquest has named Synplicity as the #1 provider of PLD synthesis tools, announcing a 54 percent market share in 2001, the last year for which data is available. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs), structured ASICs and system-on-chip (SoC) integrated circuits. The company’s fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of March 31, 2003, Synplicity employed 261 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com

The specific features, functionality and release timing of any new products or new versions of current products remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if specific features, functionality or releases may occur as described in this press release.

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Synplicity, Amplify, Behavior Extracting Synthesis Technology and Physical Optimizer are registered trademarks of Synplicity Inc. Amplify ASIC, BEST and Physical Analyst are trademarks of Synplicity Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.