Synplicity Enhances RTL Prototyping Software with Key Improvements
Company Upgrades ASIC Conversion and Synthesis Capabilities; Adds New Device and Operating System Support to Its Certify Software

SUNNYVALE, Calif., February 18, 2003 — Synplicity, Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced it has enhanced its Certify® verification synthesis software to ease the ASIC prototyping process and improve quality of results (QoR). This new version of the Certify software offers advanced ASIC verification capabilities that provide designers with increased visibility into the prototyping process, including gated-clock reporting and source-code level partitioning. The company also added a new timing engine and timing analysis capabilities, as well as support for Altera Corporation’s (Nasdaq: ALTR) high-performance Stratix™ devices and the Linux operating system, among other enhancements. With these enhancements, Synplicity believes designers can realize significant benefits in time savings, a requirement in creating high-performance ASIC prototypes.

“With ever-increasing non-recurring engineering costs and mask expenses, today’s market environment favors cost-effective ASIC verification solutions, driving customers to look at prototypes as an alternative to lower performance or more expensive technologies,” said Brian Caslis, director of marketing for the Certify product line at Synplicity. “We believe this enhanced version of the Certify software is our highest performance verification synthesis solution to date and that its advanced features will meet the needs of ASIC customers looking for robust RTL prototyping solutions.”

Enhancements to Industry’s Leading RTL Prototyping Product
Continuing to speed the prototyping process, Synplicity has enhanced the gated-clock capabilities of the Certify software to offer designers greater visibility of gated-clock elements within the prototype. A new gated-clock reporting feature allows the designer to view detailed reports that highlight specific ASIC conversion results and messages performed by the Certify software to avoid costly timing and performance problems with FPGA-based prototypes. The enhanced software now includes Synplicity’s highest performance synthesis engine available, speeding synthesis time and improving synthesis results. Synplicity has also added interactive timing analysis capabilities, enabling designers to identify critical paths quickly and perform fast, interactive timing analysis without re-synthesizing their design.
Continuing Synplicity’s commitment to support the leading edge FPGAs, the Certify software now offers support for Altera’s high-performance Stratix devices. Altera’s Stratix FPGAs offer a rich set of advanced features, such as dedicated DSP blocks and abundant on-chip memory resources, which can be leveraged for complex ASIC prototype development.

“RTL functional prototyping offers designers substantial time-to-market advantages and enables early system software debugging. Based on Synplicity’s proven synthesis technology, the Certify software delivers a unique solution for our customers designing high-performance FPGAs,” said Jim Smith, director of EDA vendor relations at Altera. “We have worked closely with Synplicity to ensure the enhancements in the Certify software will allow designers to quickly maximize the performance of our high-performance Stratix architecture.”

The Certify software is also compatible with the new DN5000K10 Stratix device-based prototyping board recently introduced by The Dini Group, a professional hardware and software design services firm specializing in high-performance digital circuit design and application development and is also one of Synplicity’s Partners in Prototyping. The Quick Partitioning Technology within the Certify software provides designers with an automated design flow for prototyping with these off-the-shelf, multi-FPGA boards, dramatically reducing time to market.

Mike Dini, president of The Dini Group said, “Synplicity’s Certify software is the only software we have found that allows designers to easily develop ASIC prototypes early in the design phase, and it is extensively used among customers of our off-the-shelf prototyping boards. Using this software along with our new Stratix device-based prototyping board, we expect our customers will be able to quickly and easily develop a high-performance prototype of their ASIC design.”

Additionally, Synplicity has enhanced the source-code level partitioning capabilities of the Certify software to allow users to generate RTL code that refers back to the source code for each FPGA after partitioning. This capability preserves the original source code, even after partitioning. To further improve design performance, the Certify software also offers enhanced integration with Synplicity’s Amplify® Physical Optimizer™ physical synthesis software. Designers can use the output from the Certify software after partitioning directly in the Amplify software to perform further timing optimizations.

Synplicity has also added support for the Linux operating system, enabling a broader range of designers to take advantage of the Certify software’s prototyping capabilities. In addition to Linux, the Certify software runs on UNIX (Solaris & HP), Windows NT, Windows 2000 and Windows XP Pro operating systems.

Other key enhancements to the Certify software include:

• Increased capacity with MultiPoint™ synthesis technology support for logical hierarchy
• Addition of support for Synopsys’s DesignWare® components in both Verilog and VHDL languages
• Enhanced Verilog 2001 language support
• Xilinx ChipScope Pro support

Pricing and Availability
The Certify 6.2 software is available now. A perpetual license of the software costs $115,000 and a one-year time base license costs $45,000. Current Certify customers on maintenance will be upgraded at no additional cost.

About the Certify Software
The Certify software is believed to be the industry’s first register transfer level (RTL) prototyping solution that enables designers to create functional hardware prototypes of their ASIC design at the RTL, prior to ASIC synthesis. Verification at this early stage of design results in a dramatic increase in productivity and enables faster time to market, especially for one-million-gate-plus ASIC/SoC designs. Synplicity believes that prototypes defined by the Certify product will enable extensive verification allowing ASIC designers to perform the following tasks at- or near-system speed: hardware/software co-verification; algorithm development and verification; verification of intellectual property, either cores or library elements; system software development and debugging, verification of system-level protocol compatibility and early system/product development with FPGAs.

About Synplicity
Synplicity, Inc. (Nasdaq: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company's industry-leading position, since the year 2000 Dataquest has named Synplicity as the #1 provider of PLD synthesis tools, announcing a 54 percent market share in 2001. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. The company’s fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of December 31, 2002, Synplicity employed over 250 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com.

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Synplicity, Amplify and Certify are registered trademarks of Synplicity, Inc. MultiPoint and Physical Optimizer are trademarks of Synplicity, Inc. DesignWare is a registered trademark of Synopsys, Inc. All other brands or products are the trademarks or registered trademarks of their owners.

Synplicity Press Contact:
Steve Gabriel
Porter Novelli
408/369-1800
steve.gabriel@porternovelli.com

Synplicity Reader Contact:
Brian Caslis
Synplicity, Inc.
408/215-6000
caslis@synplicity.com