SNUG Silicon Valley 2012 Proceedings |
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| Speeches | | Keynote Address | Critical Mass, Systemic Complexity and Innovation: Catalysts for Designing Change
Author(s): Aart de Geus, CEO & Chairman of the Board [Synopsys, Inc.] |
| | Partner Keynote | Partnering for Low Power
Author(s): John Cornish, Executive VP [ARM] |
| | Technology Keynote | 3D FinFET - New Structure Extends the Life of the Transistor!
Author(s): Chenming Hu, Professor Emeritus & Former CTO TSMC [UC Berkeley] |
| | User Papers and Presentations | | MA3 User Session: UVM Factories and USB 3.0 Verification | Integrating DesignWare USB3.0 Device Controller In a UVM-Based Testbench
Author(s): Ning Guo [Paradigm Works] |
| The OVM/UVM Factory & Factory Overrides - How They Work - Why They Are Important
Author(s): Clifford Cummings [Sunburst Design] |
| | MA4 User Session: Advanced Analysis with HSPICE & CustomSim-VCS | Statistical Margin Sensitivity to RNG option for Monte Carlo Simulations with HSPICE
Author(s): Tom Mahatdejkul, IngMing Chang, Ling Chein [ARM] |
| Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure (Technical Committee Award Honorable Mention)
Author(s): Ravi Ram, Warren Anderson, Shyam Sivakumar [Advanced Micro Devices, Inc.], Vijay Akkaraju [Synopsys, Inc.] |
| | MA6 User & Tutorial Session: Signoff-Driven Design Closure | PrimeTime DMSA ECO Fix: a Case Study
Author(s): Bo Gao, Khoan Truong, Shankar N, Hong Chen [Cypress Semiconductor] |
| | MB1 User Session: Design Correlation | Improving Virtual Route Correlation on Advanced Process Nodes
Author(s): Michael McCoy, Atul Walimbe [Intel Corp.] |
| The Impact of Correlation on Design Quality, Design Closure Loops, and Design Turn Around Time
Author(s): Iksoo Pyo, Ivan Castellanos, Atsadang Tansathit, Zhan Chen [Intel Corp.] |
| | MB3 User Session: Minimizing RTL-to-Netlist Simulations Mismatches | X-Propagation: An Alternative to Gate Level Simulation (2nd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Adrian Evans, Julius Yam, Craig Forward |
| Yet Another Latch and Gotchas Paper
Author(s): Don Mills [Microchip Technology, Inc.] |
| | MB4 User & Tutorial Session: Testability for Custom Logic & 28nm Cell Characterization Challenges | Enabling DFT Logic and Timing Verification in Mixed-Signal Designs with XA & VCS Cosim
Author(s): Bing Chuang [Rambus], Sumit Vishwakarma [Synopsys, Inc.] |
| | MC3 User Session: Enhancing Self-Checking Testbenches | A Unified Self-Check Infrastructure - A Standardized Approach for Creating the Self-Check Block of Any Verification Environment
Author(s): John Sotiropoulos, Matt Muresan, Massi Corba [Draper Laboratories] |
| Snooping to Enhance Verification in a VMM Environment
Author(s): Joseph Manzella [LSI Corp] |
| | MC5 User Session: FPGA Design | Efficient FPGA Implementation of Microprogram Control Unit Based FIR Filter using Xilinx and Synopsys Tools
Author(s): Syed Manzoor Qasim, Mohammed Sulaiman BenSaleh, Abdulfattah Mohammad Obeid [King Abdulaziz City for Science and Technology] |
| | MC7 User & Tutorial Session: UVM for ESL and HLS for Multi-Rate Communication Designs | Does UVM make sense for ESL?
Author(s): David C Black [Doulos Inc.] |
| | TA1 User Session: Low Power Design | An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys’ Galaxy Platform (Technical Committee Award)
Author(s): Jatin Mistry [University of Southampton], James Myers [ARM Ltd.] |
| PCIe Power-Gating Implementation Using Synopsys Low-Power Tool Flow
Author(s): Jason Tan, Santosh Singh, Kedar Kulkarni, Anand Iyer [Advanced Micro Devices, Inc.] |
| | TA3 User Session: UVM RAL and Solution for X Propagation | Easier RAL: All You Need to Know To Use the UVM Register Abstraction Layer
Author(s): Doug Smith [Doulos] |
| X-Optimism Elimination during RTL Verification
Author(s): Robert Booth [Freescale], Bruce Greene, Arturo Salz [Synopsys, Inc.] |
| | TA5 User & Tutorial Session: FPGA Prototyping | Slow Dancing with Memories - Sometimes it's Harder to Go Slow
Author(s): Manoj Agarwal [SanDisk], David Castle [Synopsys, Inc.] |
| | TA6 User Session: MultiVoltage and Low Power Analysis Technologies | 28nm ETM Generation with Multi-voltage Domain(UPF compliant) and Embedded IO
Author(s): Anne Yue, Bill Griesbach, WeiMun Chu [LSI Corp] |
| Early Leakage Power Estimation for Use Cases Across PVT
Author(s): Hwisung Jung [Broadcom Corp.] |
| | TA7 User Session: Designing Custom Processors as an Alternative to Fixed HW Blocks | Deploying Processor Designer for a Custom Super Scalar Processor for Software Defined Radio
Author(s): Makoto Mouri [Fujitsu] |
| Programmable Accelerator for a Mobile SoC
Author(s): Christopher K Wolf [Audience, Inc.] |
| | TB1 User & Tutorial Session: Automated Design Planning and Design Closure | Hippo Lake: A Case Study of Automated Design Planning in High Speed Designs
Author(s): Justin Barber, Victoria Kolesov, Atul Walimbe, Michael McCoy [Intel Corp.] |
| | TB3 User Session: Simultaneous C/Assembly/RTL Debug with DVE & SimpleTest Writer Interface with SystemVerilog | Integrated RTL and Software Code Debugger in DVE for Verification of an ARM-Based SoC
Author(s): Noumaan Shah [Broadcom Corp.] |
| Mechanism to Allow Easy Writing of Test Cases in a SystemVerilog Verification Environment, Then Auto-Expand Coverage of the Test Case
Author(s): Ninad Huilgol [VerifySys] |
| | TB5 User & Tutorial Session: FPGA Prototyping | Functional Coverage for FPGA Prototype Validation Offers a New Verification Paradigm
Author(s): Seonil Choi, Sivakumar Ramakrishnan [Intel Corp.] |
| | TB7 User Session: Early SoC Architecture Performance Analysis | Architecture Analysis of a Multi-Mode Base-Station Chipset
Author(s): Dr. Andrea Kroll, Qiang Wang [Futurewei Technologies, Inc.] |
| SoC Architecture/ Performance Modeling using SystemC/TLM 2.0, a Case Study using Synopsys Platform Architect
Author(s): Ali Poursepanj [LSI Corp.], Anthony Fama [Synopsys, Inc.] |
| | TC2 User Session: Clock Tree Design | Gater Expansion with a Fixed Number of Levels to Minimize Skew
Author(s): David Chinnery, Shitanshu Tiwari, Peter Osler, Michael Scott, Hai Vo-Ba [AMD], Ron Halliwell [Synopsys, Inc] |
| | TC5 User & Tutorial Session: FPGA Design | Unleashing the Power of the Command-Line Interface
Author(s): Jeremy Webb [Centellax, Inc.] |
| | WA1 User Session: Design Planning | Developing and Implementing a Flip Chip Interface using IC Compiler (3rd Place - Best Paper)
Author(s): Prasanth Koduri, Sampath Oks, Anupam Gangopadhyay, Santhosh Pillai [Samsung], Susheel Sharma [Synopsys, Inc.] |
| Powerful things you can do with Template-Based Power Network Synthesis combined with Basic Polygon Operations in IC Compiler
Author(s): Johnie Au [Cypress Semiconductor] |
| | WA2 User Session: Optimizing Test Time with SerDes and Manufacturing Data Analysis with Yield Explorer | Commonality Analysis with Yield Explorer
Author(s): Bharath Seshadri, Puneet Gupta, Vishal Mehta, Bruce Cory [NVIDIA Corp.] |
| Optimizing Test Times using a Scan Deserializer/Serializer Architecture (1st Place - Best Paper, Best First-Time Presenter)
Author(s): Milind Sonawane, Jonathon E Colburn, Amit Sanghani [NVIDIA Corp.] |
| | WB2 User Session: Power Efficient Clocking for Test and Custom Scan Chain Stitching with DFTC | Power-Efficient Functional and Scan Clocking for High Performance Cores
Author(s): Martin Amodeo, Dwight Elvey [AMD], Aurelia De Colle, Lori Schramm, Tim Ayres [Synopsys, Inc.] |
| Scan Stitching Separate Groups of Mux-D or LSSD Flops
Author(s): David Chinnery, Kedar Kulkarni, Tejinder Jaswal, Umesh Chejara, Pawan Panday, Nethra S Gopal, Girish T Prabhakara [Advanced Micro Devices, Inc.] |
| | Publication Only | | Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking
Author(s): Kesava R. Talupuru, Sanjai Athi [MIPS Technologies] |
| Analyzing AOCV GBA Pessimism Reduction and AOCV Block Based Derate in 2011.12 PrimeTime
Author(s): Alexander Tetelbaum [LSI], David Keyser [Synopsys, Inc.] |
| Clock gating: Comparing Effectiveness of Manually Inserted versus Power Compiler Inferred
Author(s): Nanda Lekkelapudi, Maya Mohan [MIPS Technologies] |
| Efficient implementation for multi-channel FIR filters using Synplify Pro for the new mid-range Lattice FPGA devices
Author(s): Nilanjan Chatterjee, Asher Hazanchuk [Lattice Semiconductor Corp], Hariharan Sankaran Ph.D., Amit Roy, Madhav Chikodikar [Synopsys (India) Pvt. Ltd.] |
| Oh Boy, Chip Area Blows-Up Again!
Author(s): Ang Boon Chong, Loh Phooi Choong [Intel], Keith Duwel [Altera] |
| SoC performance evaluation using high performance SystemQ and TLM models for communications SoCs
Author(s): Rocco Jonack [Sonics, Inc.], Bernhard Keppler, Dr. Renate Henftling [Lantiq GmbH] |
| Using IC Compiler for Signal EM Fix in 28nm
Author(s): Kevin Huang, James Deng [Altera] |
| | Tutorials | | MA1 Tutorial | Galaxy RTL: Design Compiler Family Update
Author(s): Sal Tiralongo, Erin Hatch [Synopsys, Inc.] |
| | MA2 Tutorial | IC Compiler Custom Co-Design
Author(s): Ed Lechner, Denis Goinard [Synopsys, Inc] |
| | MA6 User & Tutorial Session: Signoff-Driven Design Closure | ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Author(s): Vivek Ghante [Synopsys, Inc] |
| | MB2 Tutorial | Accelerating Manufacturing Closure at 28nm and below with IC Validator and In-Design Technology
Author(s): Ron Duncan [Synopsys, Inc.] |
| | MB4 User & Tutorial Session: Testability for Custom Logic & 28nm Cell Characterization Challenges | Standard Cell Library Characterization Flow using Liberty-NCX and HSPICE
Author(s): Sheela Shreedharan [Synopsys, Inc.] |
| | MB5 Tutorial | Design Reliability Challenges for 28nm and Beyond
Author(s): Meera Srinivasan [Synopsys, Inc.] |
| | MC1 Tutorial Session: Design Correlation and Flipchip Package Design | A Chip-Package Design Flow Using Zuken and Synopsys Tools
Author(s): Kazunari Koga [Zuken], Frank Malloy [Synopsys, Inc.] |
| Intelligent and Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes
Author(s): Shoukyou Wang, Changge Qiao [Synopsys, Inc.] |
| | MC2 Usertorial Session: IC Validator | Enabling DRC+ Pattern-Based Physical Verification with IC Compiler and IC Validator
Author(s): Luigi Capodieci [GLOBALFOUNDRIES] |
| Optimizing Design Fill at 28nm and below using In-Design Physical Verification with IC Validator
Author(s): Norma Rodriguez [Advanced Micro Devices] |
| | MC4 Tutorial | How to Get the Most from Your Circuit Simulation
Author(s): Szekit Chan, Tom Hsieh [Synopsys, Inc.] |
| | MC6 Tutorial Session: Static Timing Technology | Galaxy Constraints Analyzer: Comparing Multiple SDC Constraints Files
Author(s): Lionel Corbet [Synopsys, Inc.] |
| Performance and Productivity Improvements in PrimeTime 2011 Releases
Author(s): Jayant Joglekar [Synopsys, Inc.] |
| | MC7 User & Tutorial Session: UVM for ESL and HLS for Multi-Rate Communication Designs | Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design
Author(s): Doug Johnson [Synopsys, Inc.] |
| | TA5 User & Tutorial Session: FPGA Prototyping | Determining Optimal FPGA System Connectivity
Author(s): Joseph Marceno [Synopsys, Inc.] |
| | TB1 User & Tutorial Session: Automated Design Planning and Design Closure | Faster Top Level Closure With Transparent Interface Optimization (TIO)
Author(s): Radhika Shankar [Synopsys, Inc.] |
| | TB5 User & Tutorial Session: FPGA Prototyping | Effective Strategies for Bringing Up and Debugging an FPGA-Based Prototype
Author(s): Nathan Henderson [Synopsys, Inc.] |
| | TB6 Tutorial Session: Parasitic Extraction for Emerging Technologies | Dealing with Metal Fill in 28nm ECO Extraction Flows
Author(s): Vishal Kedia [Synopsys, Inc.] |
| Double-Patterning Aware Extraction and Timing Signoff at 20nm
Author(s): Baribrata Biswas [Synopsys, Inc.] |
| How do FinFETs Impact Parasitic Modeling and Extraction?
Author(s): Baribrata Biswas [Synopsys, Inc.] |
| | TC1 Tutorial & Panel Session: Optimized Implementation for High Performance Cores | Techniques for High Performance Cores using Synopsys Galaxy Platform-ARM® Cortex-A15 Case Study
Author(s): Daniel Biset, Man-Fai Shek [Synopsys, Inc.] |
| | TC3 Tutorial: ARM AMBA 4 ACE VIP and Low-Power Simulation Debug | Achieving Rapid Verification Convergence with ARM(R) AMBA(R) 4 ACE(TM) VIP
Author(s): Tushar Mattu [Synopsys, Inc.] |
| Debugging Low-Power Simulations
Author(s): Ajay Thiriveedhi [Synopsys, Inc.] |
| | TC4 Tutorial | Test Updates, Yield Improvement, and the Importance of Standards
Author(s): Adam Cron Yervant Zorian, John Kirkland [Synopsys, Inc.] |
| | TC5 User & Tutorial Session: FPGA Design | Solving P&R Challenges on High Density Xilinx FPGAs
Author(s): Chris Dunlap [Xilinx] |
| | TC6 Tutorial Session: Signoff using Formal Equivalence Checking | ESP Memory Redundancy Verification
Author(s): Dave Hedges [Synopsys, Inc.] |
| Formality Low Power Equivalence Checking with UPF
Author(s): Erin Hatch [Synopsys, Inc.] |
| | TC7 Tutorial: Enabling Early Software Development for ARM-Based Designs | Developing Software for ARM big.LITTLE Based Designs Running Android
Author(s): Robert Kaye [ARM], Tom De Schutter [Synopsys, Inc.] |
| SoC FPGA Virtual Target: An Application of Virtual Prototyping
Author(s): Charu Khosla [Synopsys, Inc.] |
| | WA3 Tutorial | VCS Technologies and Testbench Methodologies for Achieving Higher Video Throughput
Author(s): Kiran Maiya [Synopsys, Inc.] |
| | WA4 Tutorial Session: Compute Farm Infrastructure for EDA | Optimizing Scale Out for Synopsys EDA Tools using a Common Distributed Processing Framework
Author(s): Ramki Balasubramanian [Synopsys, Inc.] |
| Rightsizing EDA Infrastructure & Impact of Low Power Processors on EDA
Author(s): Venkata Ravella, Amit Sogani [Synopsys, Inc.] |
| | WB1 Tutorial | IC Compiler: Achieving Design Success at 20nm
Author(s): Rajiv Dave, Zugang Li [Synopsys, Inc. ] |
| | WB3 Tutorial | Getting X Propagation under Control
Author(s): Bruce Greene [Synopsys, Inc.] |
| | WB4 Tutorial Session: Compute Farm Resource Usage and Optimization | Business Rules Monitoring - Automated Resource Policy Implementation
Author(s): Chris Sooy [Altera], John Mincarelli [Synopsys, Inc.] |
| Leveraging Adaptive Resource Optimization with Lynx
Author(s): John Mincarelli [Synopsys, Inc.] |
| | WC1 Tutorial Session: Advanced Multichip Design | Creating Multi-IO Ring Die Using IC Compiler
Author(s): Sufyan Khan [Synopsys, Inc.] |
| Design of a 2.5D Silicon Interposer using IC Compiler
Author(s): Frank Malloy [Synopsys, Inc.] |
| | WC3 Tutorial | VCS Technologies for Efficient Development and Debug of UVM Testbenches
Author(s): Srivatsa Vasudevan [Synopsys, Inc.] |
| | WC4 Tutorial Session: Management of High-Performance Compute Resources | Understanding the Impact of NFS Overhead
Author(s): Glenn Newell [Synopsys, Inc.] |
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