|Managing coverage grading in complex multicore microprocessor environments|
In order to deliver ever increasing performance at bounded clock frequencies, processor vendors have turned to multicore designs that allow many programs to execute in parallel on a single chip. Verification of a multicore design is substantially more complex than a single core design because access to shared resources, such as the memory and I/O subsystems, requires arbitration and coherency. Not only general purpose processors, but embedded and application-specific processors such as graphics processing units (GPU), must be verified using large regression suites.
Jan 19, 2011
|Solving Modern Verification Challenges for Today’s Industry Leaders|
Chip complexity is driving verification requirements. As process nodes continue to shrink and complexity grows, the dominant problem faced by engineering teams lies not in actually creating new designs, but in creating them correctly, on time, while managing risk.
Nov 05, 2010
|The New Economics of Verification|
A more intelligent approach to verification can help design teams control the rising cost of chip design, according to Manoj Gandhi, senior vice president and general manager of Synopsys’ Verification Group.
Sep 13, 2010
|Generating AMD microcode stimuli using VCS constraint solver|
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010
|Attacking Constraint Complexity: E Soft and SystemVerilog Default Constraints|
This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 2 of this article series focuses on explores the similarities and differences, including subtle semantic differences, between E Soft Constraints and OpenVera Default constraints in the interest of optimizing constraint performance and speeding validation.
Mar 09, 2010
|Attacking Constraint Complexity: Verification IP Reuse|
This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 1 of this article series focuses on verification IP reuse—detailing how a solver typically interprets constraints and providing a case study focused on a constraint-driven performance optimization strategy with respect to the flexible packet parser of a hypothetical networking ASIC.
Mar 02, 2010
|Formal verification with constraints: It doesn't have to be like tightrope walking|
The relentless increase in the number of transistors integrated on a single chip continues to take its toll on verification teams. Market pressures squeeze product development times, leaving little room for error.
Feb 02, 2010
|VCS Enables Efficient Constraint Solving and Debugging of SoC Design|
Yassine Even Amine, Applications Consultant at Synopsys, explains the considerations for a functional verification approach to debugging complex SoCs.
Oct 13, 2009
|Combining Formal Verification With Simulation: You Can Have Your Cake and Eat it Too! |
With ever-increasing design complexity and the desire to verify a design as exhaustively as possible, chip designers are increasingly interested in adopting formal verification methodologies.
Sep 08, 2009
|SystemVerilog and VMM Overcome WiMAX Verification Challenges|
SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker.
Aug 05, 2009
|Chip-verification and -design flow focuses on low power|
The latest generation of Synopsys’ Discovery verification platform upgrades the offering with new multicore simulation technologies, native design checks and low- power verification capabilities.
May 01, 2009
|Multicore, Mixed Signal Tools Take Center Stage|
Synopsys is beefing up its Discovery verification platform, a move that is at the forefront of a projected recovery in the electronics industry and a new push for tools that can help ease the burden of increasingly complex SoC designs.
Apr 06, 2009
|Synopsys Introduces Discovery 2009|
Platform Encompasses New Multicore Simulation Performance, Native Design Checks, Comprehensive Low Power Verification Capabilities, and CustomSim Unified Circuit Simulation Solution.
Apr 06, 2009
|Synopsys Moves Tools to Multicore Hosts|
Synopsys has increased verification speed and brought digital, analogue and memory simulation under the same roof as it moves its tools to multi-core hosts.
Apr 06, 2009
|Innovating methodology beyond base classes|
While base classes accelerate SystemVerilog deployment, the verification challenge continues to grow, and there exists a need to further advance verification productivity. Synopsys has been addressing this need by creating VMM Applications on top of the base classes that allow engineers to focus on finding bugs in their designs, instead of spending time on repetitive tasks for every project.
Jan 05, 2009
|Synopsys Tips 'Hybrid' Formal Verification|
eeDesign is the comprehensive source of information for electronics design tools and methodologies.
Nov 02, 2008
|Verification, ESL see the same future|
EEdesign runs exclusive on-line columns from Clive "Max" Maxfield and Ron Wilson, as well as EE Times columns by Richard Goering, John Cooley, and selected industry contributors.
Oct 10, 2008
|Synopsys upgrades VCS and Vera|
eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. Your feedback is welcome.
Oct 10, 2008
|Electronic Design Verification Evolves Into Lean, Mean Bug-Stomping Machines|
As chip design gets larger, verification methodologies get smarter. Not only do they help you ask the right questions, they also let you know when you've gotten all the answers that really matter.
Sep 11, 2008
|IC Journal Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation|
Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation
Aug 26, 2008
|IC Journal TCL Drives C Drives SystemVerilog|
Judging by advertising and datasheets and other promotional materials, verification is pretty much a simple, clear-cut, well-solved problem. Actually, that’s not quite true.
Aug 26, 2008
|SOCcentral Formal Verification Goes Mainstream|
Formal verification is a term that's been kicking around the EDA industry for years, but only recently has seen some success in helping designers verify their complex SOC's, processors and ASICs.
Aug 05, 2008
|SystemVerilog:The Complete Solution|
The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard,
Jul 06, 2006
|SystemVerilog reference verification methodology: ESL|
Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL).
Jun 12, 2006