More information about the Verification FastForward Migration Program

"AMD has used Synopsys VCS with OVM since 2008. The VCS SystemVerilog implementation is mature and we are happy with our decision to use the OVM framework with VCS, as we have seen improved productivity and user advantages. We look forward to moving to UVM to achieve the same advantages, along with the strength of it being an Accellera standard."
        Warren Stapleton, senior fellow at AMD.

"Network security consistently imposes more design complexity, which necessitates a high-performance, efficient, and scalable verification solution, especially given our mounting time-to-market pressures. We migrated to VCS because it offered a significant performance advantage over other solutions, and it proved a good fit for our growth plans as we move to larger designs, targeted for both high-end FPGAs and ASICs."
        Barun Kar, senior director of hardware engineering at Palo Alto Networks.

White Papers

Solving Modern Verification Challenges	English	繁體中文	日本语
Solving Graphics IC Verification Challenges	English	繁體中文	简体中文	日本语
VCS Multicore White Paper	English	繁體中文	日本语
Solving Networking IC Verification Challenges	English	简体中文	日本语
Solving Processor IC Verification Challenges	English	日本语
Solving SoC Verification Challenges	English	简体中文	日本语
VCS: Built for Tough Verification Technology Brief	English	日本语

Press Releases

• Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions on Multi-GHz RF Transceiver
• Verivue Deployes VMM and Synopsys VCS Solution for Verification of Scalable Media Distribution Switch
• Tego Standardizes on VMM and Synopsys VCS Solution to Speed Verification of Radio Frequency Identification Tags
• Synopsys Delivers 2x Verification Speed-up with VCS Multicore Technology
• NextIO Standardizes on VMM Methodology and Synopsys VCS for Next-Generation I/O Virtualization Chip
• Radiospire Standardizes on Synopsys VCS and VMM Methodology for Next-Generation AirHook Chipset Designs

Articles

• VCS Enables Efficient Constraint Solving and Debugging of SoC Design
• Attacking Constraint Complexity: Verification Reuse
• Attaching Constraint Complexity: E Soft and SystemVerilog Default Constraints
• Multicore, Mixed Signal Tools Take Center Stage
• Synopsys Introduces Discovery 2009

Webinars

• New Advancements in Verification Methodology (VMM and UVM)
• VCS Coverage Driven Verification
• Transaction-level Debug Using VCS
• The VCS Discovery Visualization Environment (DVE)
• Leveraging Constraint Solver Technology in VCS
• Achieving 2x Verification Speedup with VCS Multicore

Other Links

• VCS Datasheet
• Verification Martial Arts Blog