|Verilog-to-Verilog Equivalence Checking Using ESP|
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
|Transaction Debug with Verdi3|
In this webinar, you'll learn how to maximize your productivity by using Verdi's Transaction Debugging technology to dump, visualize and trace transactions. You'll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.
Rich Chang, Product Marketing Manager for Debug, Synopsys
May 22, 2013
|A Hierarchical, Low Power Design Approach for Gigascale Designs|
This webinar will help you understand the best practices for implementation of a Multi-Voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Apr 24, 2013
|Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily|
Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Aditya Kher, Senior Corporate Application Engineer (CAE), Low Power Verification, Synopsys; Harsh Chilwal, Senior R&D Engineer, Synopsys
Apr 04, 2013
|Accelerate PCIe Integration Testing with Next-Generation Discovery VIP|
Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.
Neill Mullinger, Product Marketing Manager, Synopsys; Paul Graykowski, Corporate Application Engineer (CAE), Synopsys
Mar 20, 2013
|Functional Signoff: Measuring and Improving Verification Quality to Ensure Bug-Free Designs|
In this webinar you will learn how Certitude Functional Qualification can be added to traditional coverage techniques, to provide unique insight into the quality of RTL simulation and formal verification environments. Certitude uses a proprietary mutation-based process to insert “artificial bugs” or faults into the design and measure the ability of your existing verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality – the ability of the environment to activate, propagate and detect potential bugs – and identify specific holes and weaknesses like incomplete test scenarios, missing checkers and assertions, or infrastructure problems that can allow RTL bugs to slip through the process undetected. Fixing these weaknesses makes your verification environment stronger and reduces the risk of signing off or taping out with functional bugs.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; George Bakewell, CAE Director, Verification Group, Synopsys
Jan 10, 2013
|Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification|
This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. Learn how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. We also cover advanced VIP features, including test suite and debug, to accelerate productivity.
Neill Mullinger, Product Marketing Manager for Verification IP,
Synopsys; Jaspreet Singh Gambhir, R&D Manager for Verification IP, Synopsys
Dec 11, 2012
|Static Verification of Advanced Low Power Designs|
Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Vinay Srinivas, R&D Group Director, Low Power Verification, Synopsys; Prapanna Tiwari , CAE Manager, Low Power Verification, Synopsys
Oct 30, 2012
|New Features and Methodologies for Simplifying Hierarchical Low Power Verification with Formality|
This webinar will discuss new features in Formality to help make low power hierarchical verification easer. We will also cover how to write your power intent (UPF) to help you implement a robust, simplified, hierarchical verification flow.
Bob Hatt, Corporate Applications Engineer, Synopsys
Oct 10, 2012
|Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience|
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.
Miodrag Vujkovic, Senior ASIC Design Engineer, NVIDIA; Maria Tovey, Corporate Applications Engineer, Synopsys
Oct 04, 2012
|Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turn-around-time with VCS|
Learn how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Adiel Khan, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Oct 02, 2012
|Verification of MIPI Protocols on a Mobile Platform SoC|
This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The Webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SoC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Narasimhababu GVL, Senior R&D Manager for Verification IP, Synopsys
Aug 07, 2012
|5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study|
Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.
Francis Cheung, Senior Staff Engineer, EDA Engineering, Engineering Unit , Renesas Electronics America, Inc.; Carol Scemanenco, Senior Staff Engineer, Implementation R&D Group, Synopsys, Inc.
Jul 31, 2012
|Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP|
Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012
|Low Power Designs Made Easy: Create, Visualize and Debug Your Power Intent|
This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Sebastian Brugnoli, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Mar 07, 2012
|Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification|
In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011
|Reduce Power Consumption 30% with Advanced Synthesis Techniques|
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. An interactive Q&A session follows the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys; Rishi Chawla, Sr. Application Engineering Manager, Synopsys
Apr 14, 2011