In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010

This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 2 of this article series focuses on explores the similarities and differences, including subtle semantic differences, between E Soft Constraints and OpenVera Default constraints in the interest of optimizing constraint performance and speeding validation.
Mar 09, 2010

This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 1 of this article series focuses on verification IP reuse—detailing how a solver typically interprets constraints and providing a case study focused on a constraint-driven performance optimization strategy with respect to the flexible packet parser of a hypothetical networking ASIC.
Mar 02, 2010

The relentless increase in the number of transistors integrated on a single chip continues to take its toll on verification teams. Market pressures squeeze product development times, leaving little room for error.
Feb 02, 2010

Yassine Even Amine, Applications Consultant at Synopsys, explains the considerations for a functional verification approach to debugging complex SoCs.
Oct 13, 2009

With ever-increasing design complexity and the desire to verify a design as exhaustively as possible, chip designers are increasingly interested in adopting formal verification methodologies.
Sep 08, 2009

SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker.
Aug 05, 2009

The latest generation of Synopsys’ Discovery verification platform upgrades the offering with new multicore simulation technologies, native design checks and low- power verification capabilities.
May 01, 2009

Synopsys is beefing up its Discovery verification platform, a move that is at the forefront of a projected recovery in the electronics industry and a new push for tools that can help ease the burden of increasingly complex SoC designs.
Apr 06, 2009

Platform Encompasses New Multicore Simulation Performance, Native Design Checks, Comprehensive Low Power Verification Capabilities, and CustomSim Unified Circuit Simulation Solution.
Apr 06, 2009

Synopsys has increased verification speed and brought digital, analogue and memory simulation under the same roof as it moves its tools to multi-core hosts.
Apr 06, 2009

While base classes accelerate SystemVerilog deployment, the verification challenge continues to grow, and there exists a need to further advance verification productivity. Synopsys has been addressing this need by creating VMM Applications on top of the base classes that allow engineers to focus on finding bugs in their designs, instead of spending time on repetitive tasks for every project.
Jan 05, 2009

eeDesign is the comprehensive source of information for electronics design tools and methodologies.
Nov 02, 2008

EEdesign runs exclusive on-line columns from Clive "Max" Maxfield and Ron Wilson, as well as EE Times columns by Richard Goering, John Cooley, and selected industry contributors.
Oct 10, 2008

eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. Your feedback is welcome.
Oct 10, 2008

As chip design gets larger, verification methodologies get smarter. Not only do they help you ask the right questions, they also let you know when you've gotten all the answers that really matter.
Sep 11, 2008

Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation The Details
Aug 26, 2008

Judging by advertising and datasheets and other promotional materials, verification is pretty much a simple, clear-cut, well-solved problem. Actually, that’s not quite true.
Aug 26, 2008

Formal verification is a term that's been kicking around the EDA industry for years, but only recently has seen some success in helping designers verify their complex SOC's, processors and ASICs.
Aug 05, 2008

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard,
Jul 06, 2006

Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL).
Jun 12, 2006

Verification remains the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks.
May 01, 2006

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks.
Mar 27, 2006

Today’s chip design requires extensive system-level simulations to ensure that the right architectural trade-offs are made. In most cases these simulations require that a substantial amount of software is executed on the simulation model of the chip to cover the required functionality.
Mar 06, 2006