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Design Analysis 

Avoid wasted simulation time. Better mixed-signal chips... faster! 

Synopsys Analysis and Debug products provide a unique approach to transistor-level verification that enables engineers to efficiently analyze and debug complex AMS systems-on-chips (SoCs). CustomExplorer addresses the need for an effective transistor-level debugging environment. The tools provide a netlist-driven debugging and visualization modules, and Custom WaveView with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.

  • Tools
 

 
Circuit Check increases verification coverage and discovers potential trouble spots that simulation misses.

  • HSIMplus
  • Analysis of post-layout parasitic effects and device reliability more

 
Dynamic IR drop and electromigration analysis of power and signal nets with post-layout acceleration. HCI/NBTI impact on MOSFET aging and device reliability.


 
Debugging environment with pre-simulation Spice-centric productivity resources, netlist debugging and extensive post-simulation waveform analysis/reporting.


 
Post-simulation high-performance analog / mixed-signal waveform analyzer.



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