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Multi-Gigabit Signal Integrity Analysis with HSPICE
Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.
Scott Wedge, Ph.D, Sr. Staff Engineer, Synopsys
Aug 18, 2010 | | | Find Electrical Violations Before Tapeout with CustomSim Circuit Check
Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.
Bradley Geden, Product Marketing Manager, Synopsys
Jul 21, 2010 | | | Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis
Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.
Bradley Geden, Product Marketing Manager, Synopsys; Tom Hsieh, AMS CAE, Synopsys
Mar 25, 2010 | | | CustomSim for Memory Timing & Power Analysis
This webinar highlights memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 15, 2009 | | | Extraction Techniques to Accelerate High-Capacity Simulation
StarRC can enable up to 10x speed-up in simulation runtime while preserving golden accuracy. In this webinar our experts explain innovative techniques to boost simulation performance and capacity for your custom digital, memory or AMS designs.
Synopsys
Sep 22, 2009 | | | HSPICE StatEye – ISI Predictions Made Easy
Are your high-speed serial link simulations taking too long? Want to speed up your eye diagram generation and ISI predictions by 100X? If so, learn how to speed up high-speed serial link analyses and get the most out of the statistical eye diagram capability in HSPICE.
Christopher Labrecque, Marketing Manager, Synopsys
Apr 29, 2009 | | | Increase Design Confidence with CustomSim
Learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.
Synopsys
Apr 28, 2009 | | | Robust SI Analysis of a DDR2 Interface with HSPICE
For years designers around the world have trusted HSPICE for their signal integrity simulation needs
Dr. Scott Wedge, Senior Staff Engineer, Synopsys; Ted Mido, Senior Staff Engineer, Synopsys
Feb 13, 2007 | | | Predicting PLL Phase Noise & Jitter with HSPICE RF
Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design.
Dr. Scott Wedge, Senior Staff Engineer, Synopsys
Jan 03, 2007 | | |
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