Physical Implementation 

Next-generation Physical Design System 
Physical implementation in the Galaxy™ Implementation Platform provides an industry-leading, production-proven solution for physical design called IC Compiler. IC Compiler is a comprehensive place and route system that includes Extended Physical Synthesis, signoff-driven closure with PrimeTime and StarRC™, advanced yield optimization, physical power, physical DFT and complete design planning for both flat and hierarchical design.

 

 
IC Compiler is an integral part of the Synopsys Galaxy™ Design Platform that delivers a complete design solution
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  • Talus
  • Netlist-to-GDSII implementation for designs at or above 28nmmore

 
Netlist-to-GDSII implementation for designs at or above 28nm
Key Benefits
  • Complete netlist-to-GDSII solution for best Quality-of-Results and Time-To-Results
  • High throughput for designs in mainstream technologies
  • High performance for advance silicon technologies
  • Comprehensive optimization capabilities meet timing, area, power, signal integrity, routability and yield objectives
  • Provide predictability during the implementation process
  • Tightly correlated with golden sign-off solutions: PrimeTime SI and Star-RCXT
  • Comprehensive low power including support for multi-voltage designs, MTCMOS, leakage, dynamic optimization and low power CTS
  • Production proven at 45nm and below
  • Concurrent design planning solution for hierarchical and flat designs
  • Zroute multi-threaded technology is 10X faster, enables concurrent DFM optimizations and supports advanced routing rules
  • MinChip automated technology enables smallest routable die size
  • Supports physical test-optimized flow with DFT Compiler and DFT MAX features
  • Easy to Use with powerful GUI and Tcl support throughout
  • Supports industry standard input/output Interfaces


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