IC Compiler In-Design Technology Delivers Improved Productivity For Faster Design Closure

At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.

Traditional implement-then-verify approaches result in lengthy design iterations due to late-stage surprises. IC Compiler’s In-Design technology dramatically reduces such iterations by enabling signoff accurate analysis and physical verification during design. IC Validator, EDN Innovation award-winning physical verification tool from Synopsys, unites the worlds of physical design and verification. Working in concert with IC Compiler, IC Validator allows physical designers to efficiently conduct signoff-quality verification during the design process, and ultimately results in a DRC-clean design that passes final signoff with ease.

DAC 2009: IC Compiler Ecosystem Customer Luncheon

Faster Turnaround Time with In-Design Physical Verification Speakers: John Chilton, Moderator Sr. VP of Marketing & Corporate Development, Synopsys Antun Domic Sr. VP and General Manager of the Implementation Business Unit, Synopsys IC Compiler In-Design Technology Download Presentation Davide Casalotto Design Methodologies Project Leader, STMicroelectronics Improving Design Turnaround Time with In-Design Physical Verification Download Presentation Ed Roseboom Member, Technical Staff, AMD Benefits of Signoff Tools in Physical Design Download Presentation Kyle Peavy Physical Design Engineer, Texas Instruments In-Design Physical Verification for Faster Time to Tapeout Download Presentation Koki Tsurusaki Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics Shorter Turnaround Time (TAT) with In-Design Physical Verification Download Presentation Tom Luczejko Principal Engineer, LSI Corporation In-Design Physical Verification (PV) for Improved Designer Productivity Download Presentation Harpreet Gill Senior Engineering Manager, System LSI SoC R&D, Samsung Electronics Automated and Predictable Design Closure with In-Design Physical Verification Download Presentation