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Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping
See examples of how FPGA-based prototyping can be used to deal with the high data rates of multi-channel, wideband digital systems while reducing systems validation and hw/sw integration costs.
Neil Songcuan, Product Marketing Manager, Synopsys; Gary Goncher, Applications Engineer and System Architect, Tektronix
Jan 11, 2012
 
Divide and Conquer: Faster FPGA Delivery using Hierarchical, Parallel Design Development
Lean how to use "divide and conquer" hierarchical approaches for parallel machine execution or team-based design, and how to develop, tweak and debug your FPGA design efficiently.
ngela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Sep 20, 2011
 
How to Enable Prototyping of Multi-Million ASIC Gate Designs
Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug and development for much larger SoC projects than ever before. The webinar introduces this addition to the HAPS family and provides an overview of the complete solution. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.
Mick Posner, Product Manager FPGA-based prototyping Solutions, Synopsys
Jul 21, 2011
 
Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs
Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the result of your design implementation before you deploy your FPGA-based system.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation
Jul 14, 2011
 
Advanced Capabilities and Design Interaction with FPGA-Based Prototyping
In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. Discover how the advanced capabilities of Synopsys HAPS(R) High-performance ASIC Prototyping System(TM) and the new Universal Multi-Resource Bus interface (UMRBus) improves the overall design, verification and software development of an ASIC or SoC.
Mick Posner, Product Manager FPGA-Based Prototyping Solutions, Synopsys
Feb 24, 2011
 
Team Design for Large FPGA Projects
Team design for FPGAs can be a confusing process if you don't have the right tools and infrastructure in place. Join Amelia Dalton from TechFocus Media as she chats with Jeff Garrison, Director FPGA Implementation Marketing about the unique challenges facing design teams as they take advantage of the incredible power of today's huge FPGAs.
Jeff Garrison, Synopsys
Jan 20, 2011
 
Complementing Emulation with FPGA-Based Prototyping
Discover how FPGA-based prototyping is used as a natural progression to complement emulation when the shortening of development time is critical to the overall success of ASIC and SoC projects.
Neil Songcuan, Synopsys
Mar 31, 2010
 
The Big Design Squeeze: How to get faster design turns in FPGA-based designs
Whether you are using FPGAs to verify your ASIC or as a final implementation platform, this webinar will illustrate techniques to help you speed up your synthesis iterations by a factor of 2 vs. traditional approaches, and achieve up to 2 times the turnaround time from RTL to board with better results stability from one run to the next. Techniques for more efficient debug and optional team design techniques are also covered.
Angela Sutton, Synopsys
Mar 03, 2010
 
Low Power Algorithm Exploration
Learn how to use the Synphony high-level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink.
Chris Eddington, Director of Product Marketing, Synopsys; Josefina Hobbs, Technical Solutions Architect, Synopsys
Jan 19, 2010
 
Achieving predictable success in FPGA Projects
This 3-part series introduces Synopsys tools for FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.
Doug Amos and Paul Schoukroun, Synopsys
Mar 09, 2009
 


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