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Get the Most from Your HSPICE Simulation
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011 | | | Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011 | | | Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle
Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011 | | | Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra
Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.
Duncan McDonald, Product Marketing Manager, Synopsys; Dwayne Holst, Corporate Applications Engineer, Synopsys
May 11, 2011 | | | Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques
Learn about new time-domain noise analysis approaches available in HSPICE, and how transient noise analysis can verify critical timing and noise performance characteristics.
Scott Wedge, Sr. Staff Engineer, Synopsys
May 04, 2011 | | | Advances in Circuit Analysis with the Custom Designer Simulation and Analysis Environment
Learn how to efficiently use Custom Designer's SAE in conjunction with HSPICE and Custom WaveView to analyze a design across process and parameter variations.
Kristin Beggs, R&D Engineer, Synopsys
Oct 27, 2010 | | | Accelerate Analog Simulation with HSPICE Precision Parallel Technology
Learn how HSPICE Precision Parallel technology accelerates verification of analog/mixed-signal circuits up to 7X on 8 cores while maintaining gold-standard accuracy.
Hany Elhak, Product Marketing Manager, Synopsys; Fredrik Ivarsson, Corporate Applications Engineer, Synopsys
Oct 20, 2010 | | | Multi-Gigabit Signal Integrity Analysis with HSPICE
Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.
Scott Wedge, Ph.D, Sr. Staff Engineer, Synopsys
Aug 18, 2010 | | | Find Electrical Violations Before Tapeout with CustomSim Circuit Check
Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.
Bradley Geden, Product Marketing Manager, Synopsys
Jul 21, 2010 | | | Eliminating Late-Stage DRC Surprises with In-Design Physical Verification
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010 | | | Shaping the Perfect Audio Codec: How Your SoC Can Benefit from the Right Audio Functions’ Line-Ups
In this webinar, you will get an overview of a wide range of audio functions that can be optimized for low power consumption and small silicon area such as volume control, high isolation inputs, crosstalk, headset drivers, Class-G, pop-noise suppression and clock management. You will also learn how to select the right analog audio block lineups for different types of applications, and you will understand how Synopsys’ high-quality DesignWare Audio IP solutions can deliver performance levels at par with those from discrete components
João Risques, Product Marketing Manager , Synopsys
Apr 13, 2010 | | | Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis
Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.
Bradley Geden, Product Marketing Manager, Synopsys; Tom Hsieh, AMS CAE, Synopsys
Mar 25, 2010 | | | Custom Designer: Advances in Custom Layout Automation with SmartDRD
SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.
Marc Swinnen, Sr. Product Marketing Manager, Synopsys; Christopher Shaw, Technical Marketing Manager, Synopsys
Mar 23, 2010 | | | HSPICE/Custom Designer for Analog & RF Circuit Design
Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, Synopsys; Fredrik Ivarsson, Custom Design Corporate Applications Engineer, Synopsys
Nov 05, 2009 | | | Front-to-Back AMS Flow using Custom Designer
Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, Synopsys; Chris Shaw, Technical Marketing Manager, Synopsys
Nov 03, 2009 | | |
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