FPGA-Based Prototyping  

Scalable Prototyping System Accelerates Hardware and Software Development 

Many design and validation teams are increasingly using FPGA-based prototyping to meet time-to-market windows. Synopsys’ FPGA-based Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Together, our suite of tightly integrated and easy-to-use hardware plus software tools dramatically accelerate software development, hardware/software integration and system validation from individual IP blocks to processor subsystems to complete SoCs.

 
  • HAPS
  • FPGA-Based ASIC Prototyping Solutionmore

 
HAPS-DX, HAPS-70, HAPS-60 products provide an integrated and scalable hardware-software solution designed to improve ASIC design schedules and avoid costly device re-spins.


 
Partition SoC design blocks between Virtualizer™ virtual prototyping and HAPS FPGA-based prototyping environments for best overall prototype performance and availability.
PDF DOWNLOAD BROCHURE (PDF)


 
The Certify multi-FPGA implementation and partitioning tool combines RTL multi-chip partitioning with best-in-class FPGA synthesis.
PDF DOWNLOAD DATASHEET (PDF)


 
Synplify Premier software enables easy conversion of ASIC-style designs and implementation into the HAPS prototyping system.
PDF DOWNLOAD DATASHEET (PDF)


 
Automated RTL debug with simulator-like visibility into FPGA-based prototyping flows
PDF DOWNLOAD DATASHEET (PDF)


 
Enables co-simulation and transaction-based validation with Synopsys’ VCS as well as hybrid prototyping with SystemC/TLM-based virtual prototypes and other C++ model environments.
PDF DOWNLOAD DATASHEET (PDF)

Synopsys FPGA-Based Prototyping Solution Brings It All Together
The Synopsys FPGA-based prototyping solution is a complete hardware-assisted verification environment based on our HAPS® High-performance ASIC Prototyping System ™ which is supported by a comprehensive software flow including Synplify® FPGA synthesis, Certify® design partitioning, and Identify® interactive debugging software.

Synopsys’ High-Speed Time Division Multiplexing (HSTDM) technology combined with high-speed HapsTrak connectors ensures inter-chip communication is not a bottleneck. The fastest FPGA silicon, sophisticated PCB technology and advanced power and heat management ensures a stable and repeatable platform suited to all design types. The unique Universal Multi-Resource Bus (UMRBus) improves designer productivity by extending the rapid system prototyping environment and enabling it to be leveraged earlier in the design cycle. The UMRBus also enables remote hardware access, data streaming, co-simulation, transaction-based verification and links both our virtual prototyping and FPGA-based prototyping environments utilizing the industry standard SCE-MI interface.

Benefits of the Synopsys FPGA-based prototyping solution include:
  • Early embedded software development speeds design schedules by 3-6 months
  • Easy integration of pre-tested DesignWare IP components eliminates the need for designers to verify their IP
  • Modular platform enables reconfigurability and reuse across multiple projects
  • Proven solution with over 2500 systems used by more than 300 customers
  • High-performance prototyping system allows developers to perform real-world testing with real-world high-speed interfaces
  • Low cost and proven prototyping technology reduces schedule risk and shortens product development time for faster time-to-market
  • Easily and cost effectively deployable to software development teams worldwide
  • Co-simulation capabilities enable faster development and greater debug visibility
  • Transaction-based verification allows the prototyping system to be used as a model in system-level virtual platforms
  • Immediate availability of affordable, reliable, flexible, and expandable prototyping hardware
  • Flexible architecture supports multiple systems and high-speed interfaces
Synopsys’ FPGA-based prototyping systems are used when synthesizable RTL models of the ASIC/system-on-chip design are available, allowing designers to develop software, verify SoC hardware and enable hardware/software integration before the silicon is taped-out. Hardware and software design teams can deploy HAPS® systems in a variety of roles in the SoC development cycle.

IP Development:
HAPS systems enable designers to confirm whether an RTL block is functionally correct at much higher speeds than traditional ASIC hardware emulation. HAPS systems ease initial system bring-up by executing a single IP module or subsystem with clock and reset synchronized with an HDL simulator. In addition, designers can use existing test benches for stimulus or in a free-running mode with PLL-sourced clocks to achieve the multi-megahertz performance required in real world I/O interfaces.

Hardware/Software Co-Development:
By using a high-performance prototype, software development can begin much sooner in the design process. A HAPS series system can achieve a typical clock frequency of 50MHz, making it feasible for SoC designs to execute the low-level firmware of the software stack, as well as the full operating system and even applications. When coupled with a Virtualizer™ virtual prototype, HAPS’ RTL subsystems run concurrently with SystemC/TLM-based processor models, creating a unique and powerful hybrid prototype that delivers the best of virtual and hardware prototyping methods.

End User Evaluation:
HAPS systems are light and portable. They can be powered with conventional power sources and quickly assembled in the field for customer demonstrations, industry conferences, “plug-fests”, and validation scenarios outside of the lab environment.

Synopsys’ FPGA-based prototyping solutions enable pre-silicon embedded software development and hardware/software integration of complete systems and subsystems at near real-time operating speeds using real-world interfaces. The HAPS® High-performance ASIC Prototyping System™ is designed to support all of your ASIC prototyping needs, including hardware/software co-development, proof-of-concept studies, IP development and end-user evaluations. HAPS FPGA-based prototyping system capabilities include:
  • Flexible, scalable and expandable system architecture – maximizes the reusability for multiple projects
  • Best-in-class quality and reliability – ensures the highest system performance and stability
  • HapsTrak standard – I/O connector standard that allows for backward and forward compatibility with previous and future generations of HAPS FPGA-based prototyping systems
  • High-speed Time-Domain-Multiplexing (TDM) – high-speed interconnect multiplexing increases bandwidth limiting effective capacity on FPGAs
  • Advanced verification functionality – includes co-simulation, transaction-based verification, and fast Universal Multi-Resource Bus (UMRBus) interface for high-speed design interaction and monitoring
  • DesignWare IP Portfolio – pre-tested IP configurations

Visit the HAPS FPGA-based prototyping webpage for more information.

Synopsys’ FPGA-based prototyping software tools provide engineers with design planning, logic synthesis, debug, and verification tools to address the largest ASIC, ASSP and SoC designs. Synopsys software for FPGA-based prototyping is applied by hundreds of design teams worldwide to target the Synopsys HAPS series of FPGA-based prototyping systems as well as custom-built ASIC prototypes.

FPGA Synthesis for ASIC Prototyping
Synplify Premier software provides an ASIC compatible synthesis flow for high-capacity FPGAs. Synplify Premier offers ASIC RTL migration and optimization features ideal for engineers who target single-FPGA ASIC prototypes. Fast synthesis features speed initial bring up, DesignWare® IP compatibility minimizes the amount of ASIC RTL source design changes, and links to functional verification with VCS ease troubleshooting of design modules. Synplify Premier includes all features of Synplify Pro logic synthesis and Identify RTL debugging software.

Multi-FPGA Design Planning of ASIC Prototypes
Certify software is the leading design planning and implementation tool for ASIC designers who use advanced FPGA-based prototypes. Certify accounts for the interconnect, FPGAs, memory ICs, and clock/reset sources that comprise the prototype PCBs. Planning tools allow you to automate the assignment and partitioning of RTL and IP modules across the system. After partitioning Certify encapsulates FPGA synthesis and implementation tools to generate FPGA programming output. Certify includes all features of Synplify Premier and Identify RTL debugging software. Exclusive features for the Synopsys HAPS prototyping system minimize prototype bring-up times and deliver higher system performance.

Debug and Bring-Up of FPGA-Based Prototypes
Identify RTL debugger software allows users to instrument ASIC RTL and then, still at the RT-Level, debug the implemented FPGA on live, running prototype hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli. Exclusive features for the Synopsys HAPS prototyping system automate system bring-up and provide high capacity debug storage.

Utilities for Additional HAPS System Connectivity
The HAPS®-70 and HAPS-60 Co-Simulation (Co-Sim) and Transaction-Based Validation (TBV) Suite products are a comprehensive set of software tools and libraries that enables the connection between a HAPS-70 or HAPS-60 Series FPGA-based prototype system and a host workstation to enable hybrid prototyping, co-simulation or transaction-based verification.


FPGA-based prototyping hardware/software flow

Synopsys' offers the industry’s broadest portfolio of silicon-proven IP solutions for SoC designs. HAPS-compatible example designs are available for widely-used DesignWare IP products such as HDMI, MIPI, SATA, USB, audio subsystem and ARC processors.
Using DesignWare IP with HAPS eases common prototyping tasks, including:
  • Controller with PHY interoperability validation
  • System compliance tests
  • Subsystem integration
  • Firmware/software development

See live video demonstrations of DesignWare IP implemented on HAPS systems.

Get more detail about HAPS-series daughter boards designed for interface and SoC validation

A unified design and prototyping flow for SoC designs that integrates Synopsys DesignWare® IP eases the migration from the RTL/IP design to either an FPGA-based prototype or target ASIC silicon. The Synopsys coreConsultant tool guides the user from installation to a HAPS prototype using the Synopsys Certify® software or an ASIC implementation using Synopsys Galaxy Implementation Platform.



NewsArticlesBlogsDatasheetsSuccess StoriesWhite PapersWebinarsVideos