The Synopsys Eclypse™ Low Power Solution provides a comprehensive, silicon-proven approach to low power design that is power-aware at every stage of the design cycle. The perfect alignment of technology, methodology, intellectual property, services and industry standards, the Eclypse Low Power Solution simplifies the deployment of advanced low power design techniques.

The Eclypse Low Power Solution is built around support for industry standard IEEE 1801 Unified Power Format (UPF), the most widely adopted language to describe power intent. Spanning the entire design cycle, from early architectural and system-level analysis, to verification, RTL synthesis, test, physical implementation and signoff, the Eclypse Low Power Solution enables designers to achieve the fastest time-to-results (TTR) with the lowest risk.

Power requirements today are among the most important design considerations for electronic devices across the spectrum. From personal mobile electronics primarily focused on battery life to gigantic server farms that form the “cloud”, power efficiency is a top concern, and the distinction between classes of devices is beginning to blur. The Eclypse Low Power Solution supports a broad array of low power design techniques to enable fast, first-time success on your critical design projects.

Mobile Internet Devices – An explosion in functionality
Driven historically by battery life considerations, today’s mobile internet devices employ the latest low power design techniques to minimize leakage power, including power gating multi-Vth, and well biasing. With the recent smartphone feature explosion, however, these devices are increasingly utilizing techniques traditionally aimed at dynamic power optimization, such as, clock gating, multi-voltage design, DVFS, and others.

Digital Home – Convergence is here
As the world moves to digital television, voice and data delivery, the proliferation of digital devices in the home continues to increase. Though most home digital devices are only used a few hours a day, they continue to consume electricity 24x7. Their sheer numbers combine to create a substantial drain on the power grid. Increasing energy costs and growing concerns about sustainability have made reducing standby power a top concern.

Digital Office – Servers, clients and mobility
The typical office today is filled with digital devices, each of which is consuming power. Including devices such as copiers, fax machines, desktops, routers, tablets, phones, and others, it is no wonder that green initiatives have grown to include the digital office. Today’s digital office requirements cover the spectrum of power efficiency requirements.

Data Center – Bigger and greener
With complex load balancing and ever-increasing demand, server farms have traditionally aimed at “performance at all cost.” However, the sheer number and size of existing data centers are already straining our power grids. The EPA estimates that in the US alone, the national energy consumption for servers and data centers could reach 100 billion kWh by 2011. With demand growing, as is the desire for “green solutions”, careful planning for power and cooling is now a necessity.

Synopsys continues to champion customers' requirements for interoperability throughout the EDA industry. Interoperability is at the heart of Synopsys' solutions, design platforms, tools, and IP.

IEEE 1801 (UPF): Addressing static- or leakage-based power consumption requires new techniques and standards that fall outside the scope of traditional HDL-based flows. The IEEE Standard 1801, based on Accellera’s Unified Power Format (UPF), allows designers to describe low power design intent and improve the way complex integrated circuits can be designed, verified and implemented. Starting at the Register Transfer Level (RTL) and progressing into the detailed levels of implementation and verification, UPF facilitates an interoperable, multi-vendor tool flow and ensures consistency throughout the design process.

VMM-LP: In response to the increasing need for targeted verification of low-power IC designs, the Verification Methodology Manual for Low Power Design (VMM-LP) is now available. VMM-LP is a companion book to the Verification Methodology Manual (VMM) for SystemVerilog, which provides proven industry best practices developed since 2005. The VMM-LP methodology addresses all aspects of functional verification for designs employing power management strategies and techniques. Synopsys’ corresponding implementation of the VMM-LP base class library is also freely available. Current Synopsys customers can also download a free PDF copy of the VMM-LP here.

LPMM: The "Low Power Methodology Manual" (LPMM) is a comprehensive and practical guide to managing power in system-on-chip designs, critical to designers using 90-nanometer and below technology. Combining extensive commercial experience, deep scientific understanding, silicon technology case studies, and a pragmatic approach, the manual describes design techniques which address both dynamic and static (leakage) power, including methods for power gating and dynamic voltage and frequency scaling. Current Synopsys Customers can download a free PDF copy of the LPMM here.

The DesignWare minPower Components offer unique, power-optimized datapath architectures that suppress switching activity and glitches, reducing both dynamic and leakage power. Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, these architectures are automatically configured by DC Ultra during synthesis to implement the optimal structure with the lowest power consumption. Forty instantiable blocks that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management are also included.

Services
Synopsys Professional Services is a team of design consultants with an extensive track record of helping customers complete their cutting-edge designs. With expertise in low power tools and techniques, Synopsys consultants can help you manage your chip’s dynamic and leakage power consumption. They will help you understand the inherent tradeoffs in using power-related technologies such as clock gating, multi-voltage design, dynamic voltage scaling, multiple threshold voltages, MTCMOS power gating and IEEE 1801 (UPF). As an integral part of Synopsys, our consultants have a thorough understanding of the industry's leading low power design tools and methodologies and can assist you in deploying the latest low power techniques throughout the entire design flow, from initial design specification through functional verification, synthesis, implementation, and signoff.

Low power design is one of the fastest growing aspects of SoC design today. Though it has been a requirement for some applications, like cell phone design, it is a relatively new focus for other markets, such as digital home, office and data centers. Depending on your expertise and experience, low power design may be a relatively new specialty for you. To help bridge that gap, we’ve placed the following resources at your fingertips. These range from simple reference files, such as the low power glossary, to white papers, published articles and video tutorials.

Advanced Low Power Techniques

• Overview
• Glossary

Low Power Related Books from Synopsys Press

• Low Power Methodology Manual
• Verification Methodology Manual for Low Power
• The Ten Commandments for Effective Standards

White papers

• Synopsys Eclypse Low Power Solution
• Hybrid Techniques Reduce Dynamic Power Consumption
• Pain Management in Power Optimization

Videos

• Godwin Maben: Low Power Trends and Methodology

Webinars

• Static Verification Throughout the Low Power Design Flow
• Low Power Algorithm Exploration for ASIC Algorithm Implementation

Article

• Low Power Design is Here to Stay