In this climate, outsourcing is becoming a mandatory skill for IC-design managers. But it's not intuitively obvious. There are many reasons to consider outsourcing all or part of a chip design. Perhaps you are on a board-level-design team, and the correct approach to your new project is a chip that doesn’t today exist. Perhaps your team has previously done IC designs but lacks the skills for your next project.
Sep 03, 2009

Disaggregation of the IC and system design chain toward a specialty model has included a growing reliance on outsourcing. That has created an opportunity for developers of advanced tool suites to field design environments in which the "best of the best"--from anywhere around the globe--can be assembled for round-the-clock development of fully optimized designs.
Aug 10, 2009

With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically — making it almost impossible to test an entire design once it reaches manufacturing. But, using a core-based test strategy combined with scan compression offers one of the most effective ways to limit both huge data volumes and high power consumption of complex SoC tests.
Feb 26, 2008

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex instruction sets, multiple pipeline stages, in-order or out-of-order execution strategies, instruction parallelism, fixed- and floating-point scalar/vector operations, and other features that create a seemly never-ending list of corner cases to exercise. The time required to create traditional directed tests has become unreasonable.
Dec 10, 2007

The early years of the 21st century have seen an explosive growth in the consumption of consumer electronics and wireless communication devices. While the US continues to be the leading consumer of electronics, the growth has been fueled in part by the increased appetite for the same from double-digit growth economies such as those in India and China.
Dec 01, 2007

Deep-submicron systems-on-a-chip (SoCs) require a power-grid voltage drop of much less than 10% of VDD. Decoupling capacitors, or decaps, help achieve this goal by minimizing switching noise.
Oct 25, 2007

A chip is of little use without its software. The semiconductor industry realizes this and is more interested than ever in delivering both silicon and software at the same time. Texas Instruments has combined a number of strategies to reduce software integration time from around 18 months to just one to two months.
Oct 04, 2007

To handle numerous technical challenges associated with advanced process nodes, chip designers must have a design flow that adapts to evolving requirements and design goals. At the same time, design teams must also deal with project-related challenges, such as achieving consistent design development across geographically distributed design teams, ramping up new sites, and correcting issues with third-party-library and IP (intellectual-property) quality.
Aug 16, 2007

Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes.
Jun 05, 2007

Unless they're planned out of the design, power integrity issues like excessive rail voltage drop (IR drop) and ground bounce can create timing problems.
Jan 01, 2007

If a project goes beyond its predicted schedule, it directly impacts profitability. With this in mind, Synopsys consulting and design services organization evaluated their own physical design processes across a broad spectrum of their customer design projects to better understand how productivity can be measured and improved.
Jan 01, 2007

IC design productivity is often thought of as an elusive term. From a design team's perspective, it is a difficult concept to assess due to the fact that IC design projects are diverse in their input, application areas, and design approaches.
Oct 16, 2006

Careful power planning is essential for designs targeting advanced semiconductor processes. David Stringfellow and Kevin Knapp, design consultants with Synopsys Professional Services, give guidance on best practice recommendations that can help to ensure power integrity throughout the entire design flow.
Aug 13, 2006

When combining intellectual property (IP) blocks from various sources, you must have a complete, high-quality set of timing constraints for efficient SoC timing closure and signoff. Otherwise, IP integration problems can cause long delays.
Jul 13, 2006

The shift to smaller process geometries has led to a dramatic increase in problems due to IR drop. Michael Solka and Jonathan Young, both with Synopsys Professional Services, explain how the right IR drop target should be found before steps are taken to address the problem.
Jul 13, 2006

For many design managers, measuring design productivity may seem more difficult than improving it. While the ability to deliver increasingly complex chips all but ensures design teams are making strides toward better design productivity, quantifying this improvement can be elusive.
Mar 13, 2006

At first glance, the Pilot Design Environment from Synopsys Inc. may sound like a resurrected EDA framework from the late 1980s. But Synopsys claims to be taking a fresh approach with this integrated RTL-to-GDSII design system, sold as a customized offering by Synopsys Design Services.
Feb 27, 2006

Aimed at improving designer productivity and accelerating the tape-out of system-on-chip (SoC) designs, Mountain View, Calif.-based EDA giant Synopsys Inc. today detailed it’s an RTL-to-GDSII design system developed by its professional services group and based on its Galaxy and Discovery platforms.
Feb 27, 2006

Design-optimization methodologies and flows that use gates with two threshold voltages (VTH) can achieve excellent results for both power and timing with a high degree of automation. This dual-VTH approach has become crucial for VDSM (very-deep-submicron) chips, in which reduced VTH not only improves performance, but also increases static (leakage) power.
Feb 02, 2006

More than ever, power integrity is vital in the successful creation of today's system-on-a-chip (SoC) designs. That's because e xcessive rail voltage drop ( IR drop) and ground bounce can create timing problems.
Jan 19, 2006

Recent collaboration between UMC and Synopsys has resulted in a complete RTL-to-GDSII reference design flow, which now includes critical design for manufacturing features for UMC’s 90nm process.
Jan 13, 2006

Designers are using every design trick to reduce power in a 3G chip design. But, while cutting power, these tricks can create static timing analysis problems. Here's a look at how designers can close the timing gap in a 3G SoC.
Nov 01, 2005

In a flat design flow, placement and routing resources are always visible and available. Designers then can perform routing optimization and avoid congestion to achieve a good-quality design optimization. Yet large and optimization-intensive designs make flat design less desirable because of long tool run times and large memory-space requirements.
Jul 07, 2005

From 2001-2003, there was a downturn in semiconductor markets worldwide. Many veterans of the semiconductor industry argued – at the time – that the downturn was nothing new, that the semiconductor market has always been cyclical, and it is a function of supply and demand.
May 13, 2005