Audio requirements are soaring. Whereas audio used to be done in a few spare cycles of the main CPU, decoding today’s Blu-ray Disc 24-bit, 192 kHz high-definition audio streams, or post-processing 9.1 channel Pro Logic IIz streams, requires significant performance. An obvious solution is to offload the processing to one or more dedicated audio digital signal processors (DSPs) such as the DesignWare® ARC® AS211SFX/AS221BD Audio Processors, but this complicates system design and introduces a number of hardware and software challenges. This white paper elaborates on these challenges and presents a number of architectural solutions. In addition to the offloading complexities, this paper covers the integration of audio processing software in larger multimedia and product software stacks, by describing how to integrate audio software into popular Linux- and Android-based systems.
Ruud Derwig, Synopsys, Inc., Senior Staff

Implementing advanced audio functionality in a system-on-chip (SoC) involves integrating a range of hardware and software components, including an audio processor, audio peripherals, software drivers, and audio processing software. In this white paper, we discuss the requirements for audio solutions for processing of high-definition (HD) multi-channel audio and detail the challenges involved in building such solutions.
Pieter van der Wolf, Synopsys Inc., Senior Staff

Sigma-delta analog-to-digital converters (ADCs) deliver high resolution with low silicon area and power consumption, taking advantage of high-speed operation and digital signal processing common in modern digital system-on-chip (SoC), making them ideal for implementations in deep sub-micron processes. However designers are sometimes reluctant to use sigma-delta ADCs because of their unconventional architecture and apparently chaotic internal operation. This paper will give SoC designers a clear understanding of the workings inside sigma-delta ADCs and explain when they are a better alternative than other ADC architectures used in advanced, deep sub-micron SoCs.
Carlos Azeredo-Leme, Analog Design, Senior Staff

Although it is impossible to prevent hackers from trying to attack systems, making the wrong selection in NVM technology to store security and encryption keys can leave a system even more vulnerable to attacks. This whitepaper will help SoC designers gain familiarity with the options and trade-offs of the various NVM IP on the market today in order to make the right selection, ensuring the maximum security of their system data, by addressing: the main technologies used in NVM IP today for data storage, the common reverse engineering techniques of most concern to designers developing secure elements for NFC, and the most resistant NVM IP technology to reverse engineering schemes.
Craig Zajac, Senior Product Marketing Manager

In this case study, it was discussed how DesignWare IP was leveraged, including USB 2.0 host, USB 2.0 Hi-Speed OTG, Ethernet Controller and SATA, to meet key requirements of IP integration, verification and synthesis to complete a successful design in a short design cycle. The results are highlighted, discussing the issues and the methodology that can be used to achieve the most out of these DesignWare IP solutions, resulting in a reduced SoC design cycle.
Vijay Kumar Mathur, ST Microelectronics; Gaurav Bhatnagar, ST Microelectronics; Rohitaswa Bhattacharya, ST Microelectronics

To optimally address all the requirements for each application, there is a new generation of advanced data converter IP that includes Nyquist rate high-performance, high-speed ADC products, based on a highly optimized pipeline architecture. This paper describes the main power versus resolution trade-offs existing in the design of pipeline ADCs. It also discusses how digital gain calibration - one of the key techniques employed - eases those trade-offs, thus achieving significant improvements in power and area.
Pedro Figueiredo, Staff Engineer, Data Conversion

The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation for your application.
Jonathan Young, Brian Machesney

The audio codec creates the interface between the digital host processor and the audio transducers, such as microphones and speakers. When embedded in a SoC as an IP core, an audio codec appears as a digital block to the internal interfaces and transparently handles all the off-chip analog transducers and inputs/outputs. On the internal digital interface, it is important to understand the aspects relating audio sample rates and clocks. The clocks required by the data converters on an audio codec depend on the audio material sampling rates as well as on the clocks available on the host application and SoC. The combinations are quite complex due to the multitude of audio sample rate options and available host clocks. To further complicate matters, in audio-video applications, the audio clocks need to also be synchronized with the video clocks required by the video data converters. The digital filters process the digital samples between the digital audio interface and the audio data converters, and therefore, can perform sampling rate conversions. This paper will review the functions of digital filters in audio codecs and will illustrate how they can be used to support interfacing in a multitude of sample-rates and clock environments.
Carlos Azeredo-Leme, Analog Design, Senior Staff

As the use of non-volatile memory (NVM) intellectual property (IP), particularly reprogrammable NVM IP, expands beyond traditional embedded flash applications such as microcontrollers and into wireless, analog, micro-electro-mechanical systems (MEMS) and security applications, an entirely new audience of designers is integrating NVM. For these new users, there are various NVM IP usage models and solutions currently available that are optimized to meet the requirements of these different applications. When selecting the right NVM IP solution, designers must take into consideration the specifications associated with the NVM IP as well as its nuances and overall impact on the system-on-chip (SoC) design.
Craig Zajac, Senior Product Marketing Manager

When determining the trade-offs between application requirements versus area and power, selecting the right audio drivers has become a critical decision for SoC designers. Audio drivers must efficiently address a wide variety of loading conditions such as line loads, earphone and headset loads, passive loudspeaker loads and more. For many years, solutions consisting of a digital-to-analog converter and continuous time drivers have co-existed with digital-centric Pulse Width Modulation (PWM)-based solutions to address the breadth of different audio loads. Perhaps the most important reason associated with choosing a digital-centric PWM-based solution is the perception that being purely digital its silicon area cost is lower than the analog implementations. However, this whitepaper shows that digital-centric PWM-based solutions do at most offset cost from silicon area to external components while failing to address a multitude of equally important application requirements besides low cost.
João Risques, Product Marketing Manager

This white paper shows that the characteristics of the sampling clock may determine the system performance, and that their effect is independent of the data converter that is being used in the system rather being a function of the characteristics of the signal being processed by the system (for example, its frequency). It also identifies the main sources of this clock uncertainty (clock jitter effects), providing guidelines and rules for system engineers to understand and minimize such effects, thus assuring system performance requirements.
Manuel Mota, Technical Marketing Manager

As designers look to their next-generation network designs, they are faced with a set of new challenges when developing products that incorporate the common Ethernet interface. To maintain Ethernet as a dominate and long-lasting network interface, the latest IEEE updates, which are targeted at improving networking systems' Quality-of-Service, will be critical to meet the demands of the consumer.
Lokesh Kabra, Senior R&D, Manager; John A. Swanson, Senior Staff, Marketing Manager

Software is a critical component for the development of USB-based designs. In efforts to start software development early and to make it as productive as possible, design teams are often utilizing virtual and FPGA prototypes for software development prior to silicon. This white paper describes how virtual prototype use models for hardware/software verification and the integration of the LeCroy analyzer software into Synopsys' DesignWare SuperSpeed USB verification environments help solve SuperSpeed USB IP development challenges.
Frank Schirrmeister, Director, Product Marketing; Tri Nguyen, R&D Engineer