DDR Memory Interface IP 

DDR Solutions

Overview 

The DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR4, DDR3, DDR2, LPDDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering memory system performance of up to 3200 Mbps per bit, and verification IP.

There are six Synopsys DesignWare DDR PHY IP cores to choose from, as detailed in PHY Details tab, below.

All of the DFI-compatible DDR PHYs are supported by Synopsys' unique DesignWare DDR PHY Compiler.

Synopsys' DesignWare Universal DDR Memory Controller and Protocol Controller IP features a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA AXI/AXI4 Quality of Service (QoS) and Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs.

Synopsys is the #1 DDR IP provider for four years running. See why Synopsys is the Trusted DDR IP Partner.


DDR Complete Solution Datasheet


 

Enhanced Universal DDR Memory Controller (uMCTL2)
The uMCTL2 DDR memory controller supports the JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. ARM® AMBA® (AXI4, AXI3 and AHB) busses as well as a native bus are supported. Many enhancements for QoS and RAS features.


Universal DDR Memory Controller (uMCTL)
The uMCTL DDR memory controller supports the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. AMBA (AXI4, AXI3 and AHB) busses as well as a native bus are supported.


Universal DDR Protocol Controller (uPCTL)
The uPCTL DDR memory controller provides simple support for the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. A native bus is supported.

  • DDR4 multiPHY
  • Supports DDR4/3/3L/3U up to 2667 Mbps and LPDDR3/2 up to 2133 Mbpsmore

 
Supports DDR4 up to 2667 Mbps, DDR3/3L/3U up to 2133 Mbps and LPDDR3/2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET


 
Supports LPDDR4 and DDR4 up to 3200 Mbps, LPDDDR3 and DDR3/3L/3U up to 2133 Mbps
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Supports LPDDR3/2 and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET

  • DDR multiPHY
  • Supports LPDDR2, Mobile DDR, DDR3/3L/3U and DDR2 in a single PHYmore

 
Supports LPDDR2, LPDDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF DOWNLOAD DATASHEET


 
Supports DDR3/3L and DDR2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET


 
Area and feature-optimized IP solution operating at up to 1066 Mbps using Mobile DDR, DDR2 or DDR3 SDRAMs
PDF DOWNLOAD DATASHEET

Synopsys offers six DesignWare DDR PHY IP cores supporting various SDRAM standards and data rates as outlined below:

DesignWare DDR PHY SDRAMs Supported /
Maximum Data Rate
Interface to Memory
Controller
Typical Application
DDR2/3-Lite/mDDR DDR3 / 1066 Mbps
DDR2 / 1066 Mbps
LPDDR / 400 Mbps
DFI 2.1 Design in 65 - 40-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR support.
DDR3/2 DDR3 / 2133 Mbps
DDR2 / 1066 Mbps
DFI 2.1 Design in 65 - 28-nm that requires high performance DDR3 up to 2133 Mbps.
DDR multiPHY DDR3 / 1066 Mbps
DDR2 / 1066 Mbps
LPDDR / 400 Mbps
LPDDR2 / 1066 Mbps
DFI 2.1 Design in 65 - 28-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR/LPDDR2 support.
Gen 2 DDR multiPHY DDR3 / 2133 Mbps
LPDDR2 / 1066 Mbps
LPDDR3 / 2133 Mbps
DFI 3.1 Design in 28-nm and below that requires high-performance mobile SDRAM support (LPDDR3/2) up to 2133 Mbps and/or high performance DDR3 support up to 2133 Mbps.
DDR4 multiPHY DDR4 / 2667 Mbps
DDR3 / 2133 Mbps
LPDDR2 / 1066 Mbps
LPDDR3 / 2133 Mbps
DFI 3.1 Design in 28-nm and below that requires high-performance DDR4/3 support up to 2667 Mbps and/or high performance mobile SDRAM support (LPDDR3/2) up to 2133 Mbps.
LPDDR4 multiPHY LPDDR4 / 3200 Mbps
LPDDR3 / 2133 Mbps
DDR4 / 3200 Mbps
DDR3 / 2133 Mbps
DFI 4.0 Design in 28-nm and below, including 14/16-nm FinFET, that requires high-performance mobile SDRAM support (LPDDR4/3) up to 3200 Mbps and/or high performance DDR4/3 support up to 3200 Mbps for small memory subsystems.


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