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The Synopsys Embedded SRAM portfolio provides a full suite of memory compilers for a broad range of process technologies. The SiWare™ Memory product line deliver the smallest area and highest performance for 65 nm to 28 nm process nodes and are ideal for a wide range of applications, such as wireless, graphics and high-performance ASICS. The ASAP memory product line provides the largest selection of embedded memories ranging from 250 nm to 65 nm spanning many foundries to address density, speed and power requirements.
| | Provides a powerful dashboard that enables SoC designers to explore the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations |
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High-Density (HD), High-Speed (HS) and Ultra Low-Power (ULP) compilers optimized for area, performance or power, respectively. |
| | As an integral part of the SoC design and manufacturing ecosystem, Synopsys collaborates with foundry partners to offer comprehensive solutions for a wide spectrum of technology nodes. |
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