This quarterly newsletter provides you with the latest information on DesignWare® IP, including in-depth technical articles, white papers, videos, upcoming webinars, product announcements and more. As the industry’s trusted IP provider, Synopsys is committed to providing you with the resources you need to help you lower integration risk and speed time-to-market.
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|Tips and Tricks: Prototyping Your USB 3.0 System in a HAPS Environment - Discover tips and tricks on how to address the hardware challenges of your prototype and get it up and running as quickly as possible.|
In-Depth White Papers
MCCI and Synopsys Demonstrate USB 3.0 MTP
MCCI demonstrates Media Transfer Protocol from Synopsys DesignWare USB 3.0 controller and PHY to a Windows PC or tablet.
Why Can PHYs Have Fuzzy Eyes?
Understand the key contributors for fuzziness, like inter-symbol interference, and how to reduce those contributors.
CTLE or DFE?
The performance of a SerDes can be judged on its receiver equalization type. Learn the differences between CTLE and DFE, and when each type is preferred.
The DFE Tap Dance
The PCIe 3.0 specification defines a simple CTLE and a single-tap DFE in its base spec, but most designs use adaptive CTLE and multi-tap DFE. See how and why different numbers of taps are needed.
Equalization: Manual or Adaptive?
Understand what adaptive equalization is and how it relates to CTLE or DFE equalization in a PHY.
Minimize High-Speed PHY Risk for First Silicon Success
With the months required to design, fabricate, and test high-speed PHYs, see how designers have confidence in their designs before they see the silicon results.